PCI-SIG Updates Technology
June 4, 2014, PCI-SIG Devcon, Santa Clara, CA—Al Yanes and Ramin Neshati from the PCI-SIG described the updates, strategy, and roadmap for the PCI systems. The organization is looking at new apps and the technologies to enable those functions. The organization is growing and has a good financial status.
The emergence of IoT as a large business sector and the SoC solutions to power those apps calls for new operating modes for PCI. The existing server and PC functions are still viable and growing, but the industry is looking for other form factors and interconnection technologies. The m.2 form factor addresses the smaller footprint needs for the intermediate term, and OcuLink is a fit for non-motherboard optical interconnections.
The IoT apps need a low-power interface that can self integrate into the overall system. To enable better power efficiency, the low-power options for PCI include a 400 mV half swing mode, and L1 sub-states for almost total power-down. The sub-state link uses sideband signaling to wake up the peripheral. In addition, m-PCI uses the MIPI m-PHY to have a low-power electrical interface that retains all of the other features of PCI.
The m-PCIe interface, designed for mobile devices, is a hardware adaptation layer to help reduce power requirements while using existing IP. The only difference is the PHY, as all other electrical and software functions are from the basic PCI specs. The SIG is working on compliance and interoperability suites for this class of devices. The use of the MIPI m-PHY in gears 1,2, or 3 will grow to gear 4 when that data rate is available.
Since mobile devices need small form factors, the m.2 form factor uses thin connectors and is a replacement for the mini-PCIe modules. The result is a scalable performance for power within a flexible I/O standard. The PCI standard allows for support for wireless interfaces for Wi’Fio, BlueTooth, and other wireless LAN protocols, as well as SSDs. The single-sided modules can be directly soldered on to the board, or attached with a connector.
For the SoC, the SIG added some protocol extensions to ease integration and provide a fixed base for implementation. The existing functions for power management, error models, device drivers, auto-discovery and enumeration will remain. More details will be available at the Intel Developer Forum later this year.
The OCuLink is designed for I/O connections outside the box, and is an alternative to other optical interfaces. The cable is currently specified for operation at 8 Gbps and is capable of much higher rates. Prototypes should be available later this year for internal PCI storage functions, I/O expansion, and external PCIe-attached storage. The first units will be passive copper, and later versions will be active optical. The OCuLink will have 1, 2 or 4 ports running Gen 3.0 PCI and will be available for 1-3m runs. The interface will also support power delivery over the same cable.
The SFF 8639 small form-factor connector is a storage-specific connector that supports PCIe 3.0 up to 8 Gbps. This connector is targeted for high-density interconnects in servers and PCIe-based storage connectivity. The needs were defined by SFF and other form factors were not addressed. Specifications should be out later this year.
In the future, the need for even higher speeds is driving the development for PCIe 4.0. The initial specifications are calling for a doubling of data rates to 16G transfers per second versus the 8 for version 3.0. Currently, the changes are in the PHY and equalization but all other parameters will remain for back compatibility to existing PCI peripherals.
The main target is for big data operations needing to quickly access high volumes of data. Power is not expected to increase from current levels, and the SIG members are conducting studies into connectors, other protocol changes, and channel reach. Expectations are for a 10-12 inch run to a single connector, with a repeater/re-timer needed for longer runs. The specification is targeted for release in 2016.
