LETI-CEA 2014 Technology Review

July 8, 2014, LETI Day, San Francisco—Various executives from the research consortium LETI talked about technology platforms to address future industrial challenges. Hughes Metras opened the event with comments on the facilities and research areas within the organization.

Some key topics are in semiconductors and MEMS, which are supported by their 200 and 300mm wafer fabs operated by 1700 professionals. The platforms they address include micro- and nano-electronics, bio-electronics, chemistry and photonics. The bio programs address both clinical and medical areas. Overall, the organization tries to integrate laboratory, academic, and industrial partners in technology research at the pre-competitive product development stages.

Examples of their work are in CMOS down to 5nm with ST Micro, and IBM on fully depleted SOI. They are also working on alternatives like stacked die and through-silicon vias to provide the equivalent of a process step. They have applied their fab expertise to 28 nm FDSOI to achieve a very wide operating range, from 0.35 to 1.3 V. In photonics, they developed libraries, models, and modules to supplement the design tools and are also developing work on fiber-package interfaces.

Olivier Faynot described their monolithic 3-D approaches for further scaling. Today’s limits to scaling include costs and technology, which are increasing the cost of gates. They are building a sacrificial layer on a wafer, adding features, and face-to-back bonding another wafer to the stack. They have a PDK and a methodology for this work, which achieves an area improvement of 55 percent, performance improvement of 23 percent, and power reduction of 12 percent compared to a separate die solution. This set of improvements is the equivalent to a process node.

Some of the integration challenges are in designing for the thermal profiles, local interconnect, and low temperature processing for the second wafer attachment. Laser thermal anneal provides the upper layer transistors with better thermal stability and keeps the temperatures low enough to keep the interlayer intact. They have versions of CMOS on CMOS, and N-type over P-type devices. Since the top layer is very thin, it is amenable to SOI FIN, nano-wires, and FDSOI technologies. The optimal version seems to be N- over P-type devices. In addition, they can integrate sensors over the CMOS for heterogeneous integrated systems.

Luca Perniola discussed non-volatile memories (NVM). The increasing media types for storage have enabled memory hierarchies to help manage speed, power, and lower access times. Newer storage structures are changing to more on-chip NVM to eliminate some layers in the storage arrays. The primary technologies under investigation are charge storage like Flash and resistance switches. The work involves materials engineering, characterization, testing, modeling, and TCAD evaluations to find the best topologies and stack structures.

In other memory devices they have achieved over a billion write cycles for phase change materials. In RRAM devices, conductive bridges are getting more reliable, and they now have a good understanding of the underlying physics of the filaments. By doping the storage material at the back end of the line, they can have cut power for a write by half. Storing a bit in a conductive bridge memory takes less than 0.66 pJ at 0.2 V.

An oxide RAM allows memory to be placed on top of logic to reduce area and wire lengths for functions like FPGA programming memory. This type of application doesn’t need speed, as the programming can be fairly slow, but the power for the fabric memory is significant for a large FPGA. When the oxide RAM has a high-k dielectric like HfO2 the leakage is greatly reduced while the change in resistance goes up to 109.

Philippe Robert described a generic MEMS platform. LETI has 5 labs working on sensors, actuators, and RF devices. Their work includes packaging and interposers, characterization, and reliability. The resulting technology platform includes design and simulation tools, technology, fabs, etc. They have over 30 years of experience in MEMS sensors in thin films, bulk, surface, and now in nano designs. They have worked with startups like ARIX on gas sensors for chromatography and Wavelens on PZT variable lenses with up to 10 diopters change at 10V.

The latest efforts are in a parallel axis universal platform. The challenge for MEMS is miniaturizing the devices, which allows for greater integration and reduced costs at the tradeoff of lower sensitivity and higher noise. By integrating MEMS and nano-piezo structures, they have solved this problem by separated the mechanical and electrical characteristics. They now have accelerometers, gyroscopes, magnetometers, and are also able to include pressure sensors and microphones. They are in the process of transferring the technology to Tronics who will be producing a 6 degree of freedom device in a 4 mm2 package, and a full 9 degrees of freedom in a 5 mm2 package by 2016. The pressure sensor is like the ear, a lever is attached to the diaphragm and the resulting strain is measured in a normal strain gage configuration.

Laurent Pain presented their efforts on lithography. For CMOS designs, they are working on multiple electron beam imaging and directed self assembly, while for non-CMOS designs, they are investigating imprint technologies. The e-beam work can produce up to 10 wafers per hour with a mask-less litho matrix. Current equipment can generate up to 13, 260 beams with a spot size of 25nm. They have partners working on resist material purity and resolution improvements to 6nm.

The directed self assembly pilot line is addressing contact shrinkage and process integration. The nano-imprint work is approaching a full process and materials are developing. To date, they have applied their R&D to pilot lines to provide proof of concept and initial hardware platforms.

Chrystel Deguet finished with wafer bonding solutions and new applications for their technology. Wafer bonding has a number of classifications that may or may not have intermediate layers. Direct bonds are fusion bonds, so surface properties and preparation is critical. Other technologies include silicon-to-silicon, metal-to-metal (Cu-Cu), area bonding, III-V, and die to wafer. Polymer bonding and debonding offer lower costs than direct bonding and allow greater tolerances. The challenges for polymers include pressure, chemistries, time, temperature, and getting the thickness below 50 nm.

Some of the technologies under consideration offer different tradeoffs. Thermo-compression technologies for metal-to-metal must have well controlled pressure, time, temperature, and surface roughness. Eutectic bonding must deal with critical layer compression, and anodic bonding needs a specific glass.

There are many variables for the bonds, and the needs and considerations are application dependent. The advent of the advanced substrates for SOI, GeOI etc. offer alternatives to scaling, while devices like MEMS need hermetic seals. RF filters and piezo materials have other environmental concerns as thin films and other materials may need special characteristics.

Flexible substrates are fairly easy in silicon if you can thin the wafer or die to less than 5 microns. These types of devices are especially interesting in areas like healthcare. Their R&D with partners and suppliers enables other properties in known materials.