Phase Change Memory and its Positive Influence on Flash Algorithms
September 15, 2014, Storage Developer Conference, Santa Clara, CA—Rajagopal Vaideeswaran from Symantec looked into the future and saw flash being displaced by phase change memories. The technology offers higher speeds and IOPS, yet can be configured to be a plug in replacement for flash devices.
The NOR and NAND architectures for non-volatile memories provide users with choices for power and speed. NOR is slower than NAND for writes and consumes more power, but is faster on reads, which contributes to an overall lower power. NAND is less expensive and capable of higher densities, so the choice depends upon the intended use cases. The fundamental differences in the technologies and cell topologies requires different drivers and programming processes.
Both types of device require fairly high voltages for programming and reading, which takes a charge pump to generate the voltages and slows read and write times. The high voltage is needed to transfer electrons into or out of the floating gates and the presence or absence of charge determines if the cell is in a 1 or 0 state.
In comparison, a phase-change memory (PCM) uses a chalcogenide glass that can change state. This is the same type of material that is used in DVD-RW or CD-RW disks. Heat can change the material from an amorphous state which is high resistance and represents a 0 or to a crystalline, low-resistance state representing a 1. The crystallization process takes about 100ns. The industry has been working on the technology for a while, and continues to make advances in speed and density.
The handicaps of high programming voltages and complex silicon topography get worse as the chip lithography continue to shrink. The continued application of high voltages causes cell degradation over time, and the charge leakage corrupts the data and is exacerbated by exposure to radiation. NAND I/O interfaces are block based, so random access is very difficult. The floating gates contribute to limits on the number of read/write cycles per block, and the blocks have to be cleaned up on a regular basis which overwhelms the SSD controller. Garbage collection adds more write cycles to the block, further reducing lifetimes.
PCM offers a mix of the best of DRAM and NAND, non-volatile and low idle power with read page latencies of about 70ns, bit-level alterability, and endurance of over 106 writes. PCM will be cheaper than DRAM at lithography parity and scales to lower densities that NAND. The technology will offer many other benefits over NAND including data retention of 300 years and radiation tolerance. Some limitations for the technology include degradation due t GST thermal expansion, metal migration, data loss at high (soldering) temperatures and a need for reprogramming after solder.
One alternative to the semiconductor PCM is to use high-precision lacers to embed dots in quartz glass. Readout is via optical microscope as an input to a computer. This material has been stress tested to 1000 °C for 2 hours with no data loss. The data density ca be as high as 40MB per square inch.
The industry can leverage the technologies by taking advantage of the execute in place (XIP) feature of NOR for executables during boot. If PCM is widely deployed, exploit the bit alterability feature. The algorithms for the persistent storage will be able to eliminate the flash write amplification and garbage collection functions. At the same time, the industry has to watch the emergence of MRAM and RRAM technologies and comare heir characteristics to PCM.
