The Future for SiC ICs
September 15, 2014, Custom Integrated Circuits Conference, San Jose, CA—Tsuenobu Kimoto talked about the prospects for SiC ICs. The material is interesting for its inherent characteristics and is suitable for ICs operating at high temperatures and radiation-hard environments. The evolution from discrete power devices to ICs will require efforts to overcome the technology challenges.
Silicon carbide is proposed for many uses where silicon loses effectiveness. SiC exhibits ten-times higher critical (breakdown) electric field strength, two-times higher saturated electron drift velocity, and three-times higher thermal conductivity than Si. SiC is an exceptional wide bandgap semiconductor and the doping concentration can be controlled over more than five orders of magnitude, for both n-type (N or P doping) and p-type (Al doping).
The processes for making SiC are becoming mature and wafers are available in 100 to 150 mm diameters. The CMP processes are now in production, but one ongoing challenge is the high defect densities (103-104/cm2) in the wafers. Experience with Si indicates the possibility of other impacts to performance and reliability on the SiC materials.
To date, most of the devices are for power conversion and control. The major features of the SiC power devices are high-voltage blocking capabilities, low on-resistance, and high-temperature operation of over 300 °C. Some vertical MOSFETs exhibit 1.5 kV and 3.7 m?cm2. Trench MOSFETs offer higher packing densities and high channel mobility. A double trench device with a cell pitch of 4-5 microns produced an on resistance of 0.79 m?cm2 with a blocking voltage of 630 V. Other topologies offer even higher voltages from 15-26 KV for power transmission applications.
Cross Section SiC Lateral FET
The basic processing is not very different from that used in Si, but special care is required due to the strong bonding and chemical inertness of SiC. For example, the diffusion process is not practical for impurity doping in SiC because of the extremely low diffusion constants of impurities. Ion implantation into SiC requires post-implantation annealing at very high temperatures of 1600-1700 °C to achieve recovery of lattice damage and high electrical activation ratio (> 90%). Due to the high post-implantation annealing required, ion implantation must be the first process in SiC device fabrication, a severe obstacle for self-aligned source and drain implantations in MOSFET fabrication employed in Si technology.
High barrier heights make it difficult to form low-resistivity ohmic contacts even on highly-doped SiC. High-temperature sintering at 900- 1000 °C is required for obtaining good ohmic contacts. As a result, the metal/SiC interface after sintering is rather stable up to 500 °C. One good feature is that the material can grow SiO2, albeit at very low rates. This ability permits MOS or CMOS circuits. One large challenge is to get consistent and closely matched conductor mobility in the different materials.
The availability of complementary devices enables SiC ICs. One possibility is to make single chip inverters that include the switches, rectifiers, and gate-drive circuits. The developments in lateral SiC MOSFETS offers promise in these applications. A two zone reduced surface field device can provide high breakdown over 1580V and low on-resistance of 34 m?cm2. The conducting channel is depleted from both top and bottom and the top P-layer reduces the gate oxide field.
Research into other configurations like FET and bipolar junction transistors is continuing to enable higher levels of integration and different operating parameters. The problems are in the complicated gate drives for the BJTs and FETs. Logic has been implemented in TTL and ECL that can operate to 350 °C. The technology, while still in its infancy, needs to overcome threshold voltage stability, interconnect materials that can retain integrity at high temperatures, and packaging.
