Pericom targets timing for high speed servers
November 2014 – At the Open Server Summit in Santa Clara Pericom was showing major portions of their full server design solution. As the number of cores, high speed interfaces, memory sockets, and board sizes get larger it is becoming more difficult to get the signals across to where they are needed. While semiconductor technology is scaling the performance inside the chip, the physics realities of the board traces & sockets – their resistance ( R) , capacitance ( C) and inductance ( L) – have not changed proportionately. Furthermore, the smaller transistor sizes have less drive, so they are affected to a greater degree by these non-scalable board level elements.
To address these challenges and maintain signal integrity edge to edge on the boards, as well as support full length cable drive capability, Pericom has brought a full suite of solutions to the market for the high speed server design space. Fundamentally they are in two categories redrivers and retimers. Redrivers are essentially in-line amplifiers/buffers that restore the signal coming in to a full scale and clean output drive signal These allow for signals on lines that may address multiple speeds (up to 5Ghz lines) to operate on signals in the 500Mb-5GHz range – what goes in, goes out cleaned up. Retimers are circuits of specific function like PCIe. These have PLLs, and other timing blocks to not only amplify the incoming signal, but resynchronize the signal to the original clock at the original speed. The muxes are part of the redriver family of products.
The chips have been approved and recommended by major CPU and reference board design companies including being part of the AVL & BOM for the latest design Xeon system including XFI 10G ports. The chipsets are available in single, dual and quad channel versions and target the fastest high-speed serial protocol I/Os up to 12Gb. These solutions solve not only PCB signal degradation issues with linear ReDrivers, but also PCIe port fanout limitations, I2C and GPIO bus routing issues to multiple end points, protocol mux switching problems and provide very low jitter timing source and buffering for PCIe, Ethernet, and other specific protocols. The performance of the products include the UX XO family which provide less than 100 fS (femto-seconds) of RMS jitter for use in 40Gb Ethernet chipsets.\
To address the ‘total segment solution focus’ that is the theme for Pericom, the server/storage platform solutions include a new signal integrity family of linear ReDrivers for 8Gb PCIe3/10Gb Ethernet/ 12Gb SAS3, SATA3 and 5Gb USB3. A new mux switching family that covers 8Gb/10Gb/12Gb. A new I2C and GPIO families that offers port expander mux/level shifter/buffer functions. A new family of connectivity products for PCIe 2.0 packet switches for high port fanout. Additionally there are new Timing products that include protocol specific low jitter clock generators and buffers, as well as extremely low jitter 156.25MHz XO aimed at 10/40Gb Ethernet applications.
A stylized drawing showing potential application areas on a next gen server platform with the full suite of signal integrity, redriver, switch, connectivity and retiming solutions follows.
Pericom Next Gen Server Solutions
