Mismatch in High-K Metal Gate Process Analog Design

December 16, 2014, IEDM, San Francisco—A. Woo from Broadcom presented their efforts in design techniques to compensate for mismatch in Hi-K metal gate processes. The optimization techniques include process, layout, and design for variability.

Among the successful techniques that enhance traditional analog and RF functions in deep submicron technologies are: SoC re-architecting, digitally assisted ADC, digitally assisted DAC, and others. These techniques are enabled by the speed and integration level that the advanced deep submicron digital logic offered.

At the heart of all the success stories of analog/RF integration into deep submicron technologies are crucial analog circuit components that cannot be replaced by digital alternatives. It is important to preserve a certain level of analog capability within a process to support the SoC integration trend of the industry. Transistor matching is one of the elements in analog designs that cannot be completely replaced by digital components. We looked at MOS transistor matching for analog applications in the 28nm high-K metal gate (HKMG), gate last process. We need to understand the mismatch behavior in order to optimize the analog performance and make architectural tradeoffs for any technology node.

We studied how transistor mismatch behavior in high-K metal gate MOSFET is influenced by the layout styles that analog/RF circuits employ. Our focus is on large-scale array-style structures the MOSFET. In a HKMG MOSFET, new material for high-K and metal gate reduce some of the transistor mismatch compared to poly-SiON MOSFET, but the new process steps, such as metal gate etch and CMP, introduce new sources for transistor mismatch. Therefore, gate size, density, and density gradient to neighboring blocks can all affect transistor mismatch.

|We compared the mismatch of different W and L. In analog applications, both small gate length and large gate length mismatches are important. Long gate length MOS arrays are common in precision circuits and were used in this experiment. Some arrays are ~400 um x 250 um in dimension and some arrays are ~200 um x 200 um with controlled neighborhood blocks of 100um in the surroundings. Probes were placed such that measurements could be made at the array center and array edge locations. These arrays were varied to cover layout effects such as poly/active density and dummy fill environments.

Digital-to-analog converters (DAC) structures were based on a current steering architecture. Both NMOS and PMOS DACs were included in this study. The MOS current mirrors of the DACs are surrounded by the same number of dummy current mirrors that we use in DACs manufactured in poly-SiON gate technologies, and therefore, this experiment can be a fair comparison to previous technologies.

We chose to present MOS mismatch data collected from our DAC structures in terms of the differential non-linearity (DNL) measurement of the DACs. Differential non-linearity measures the mismatch of two adjacent MOS units and reported the result in terms of the number of the least significant bit (LSB) in the DAC output. A DAC is commonly designed to have a DNL of +/-0.5 LSB over all codes.

In poly-SiON MOS mismatch, longer gate length and increased number of MOS fingers both reduce the local mismatch variation of the devices. In our HKMG MOS mismatch data, we found that short gate length MOSFETs follow the trend of local mismatch variation reduction with an increase of the number of MOS fingers. In the case of the HKMG long gate length devices, the P-type exhibited a different trend. The mismatch increased as we increased the number of fingers. A slight VT mean shift is also observed across the wafer when the number of fingers increases. In the 400 um x 250 um MOS arrays, the poly/active area density of the arrays varied from 79/75 percent to 40/40 percent.

We compared the die-to-die variation at the lower left corner (L), center (M), and upper right (H) corner of each array. In one set of PMOS arrays, we saw the L and H location devices match well, while the M location devices demonstrated different patterns of VT distribution as a function of poly/active density percentage. In the set of NMOS arrays, we saw a slight variation of VT distribution in M locations, and poly/active density shows minor effect at the L locations.

We used the 200 um x 200 um MOS arrays to obtain the environment layout effect result. The largest contributing factor in this case study in edge-to-center variation is the type of transistor of the arrays. All the other factors do not show strong correlations to the edge-to-center mismatch.

In some 200 um x 200 um arrays we overlaid the top metal along the edge dies. The top metal overlay introduced a layout effect that causes a current increase in PMOS and current decrease in NMOS. The data could be an indication of a tensile stress induced by the top metal layout, which could influence the NMOS and PMOS carrier mobilities in opposite directions.

We have observed a much more prominent edge-to-center mismatch in the HKMG DACs. When compared to a SPICE simulation, the simulated DNL was below our silicon measurement, which agreed with our mismatch testline results. We saw that the DNL of one NMOS DAC and one PMOS DAC manufactured from one fab side-by-side with the DNL of an identical NMOS and PMOS DAC manufactured from a different fab. The NMOS DACs turn out to have less edge-to-center mismatch, and behave similarly between different fabrication sources. The PMOS DACs, on the other hand, show significantly more mismatch in one fab than the other.

The high-K metal gate process introduced a new set of challenges for analog designs which require a high level of precision in device matching when using long gate length MOS transistors. The MOS mismatch is no longer dominated by traditional processing effects, like CD control, etc. A stronger mismatch vulnerability to metallization layout effect is also observed in HKMG process. The understanding and inclusion of these extra mismatch behaviors is important in the circuit architectural design phase. For transistor matching, the support from the process technology community in implementing mismatch counter balances would also be important to continue the SoC integration trend for our industry as we move into HKMG processes.