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High-voltage Current Sensing ADC

February 23, 2015, ISSCC, San Francisco—Long Xu from Delft University described a current sensing ADC with +/- 30 V input common-mode input range. The likely applications include remote sensing, motor control, and current monitoring where weak differential signals are in a very high common-mode voltage setting.

The basic technology is to have a load at ground that converts the input into a current. This topology allows for wide common-mode input voltage and below ground common mode transients. The conventional solution is to have a wide common mode current sense amplifier in front of the ADC. Often, this is implemented as a chopper input, capacitive-coupled instrumentation amplifier.

The alternative for this work is to make a high common mode input range ADC to eliminate the front-end circuitry. Of the many possible architectures; delta-sigma, successive approximation, etc. feeding the switched capacitor circuits to block the large common-mode voltages. A typical switched capacitor integrator has issues with large offset, poor common-mode rejection ratio, and low input common-mode impedance. A simple modification of cross-coupled sampling cancels the input common mode voltage and doubles the input signal swing.

Previous versions of a high-voltage chopper suffered from very small input range of about 300 mVp-p. By cross-connecting the input switches you are note input limited by a more robust structure that can have input diodes to supply, ground, and on the inputs for protection. so the cross-coupled sampling allows for a +/- 30 V common-mode input voltage range and a 3-5 V operating range.

When a correlated double sampling and cross-coupled sampling are combined ahead of a delta-sigma ADC, the complex input stage reduces offset and 1/f noise in the amplifier. See figure 1 for phase and switch operation,

Figure 1: The cross-coupled inputs and bi-phase operation are shown
and figure 2 for a simplified schematic of the full delta-sigma modulator.
Figure 2: The simplified schematic of the ADC shows all the various stages and the feedback paths.

The overall performance of the design meets or exceeds all of the design requirements and are as follows:
Supply voltage: 5 V
Input common-mode range :+/- 30 V
Input differential-mode range: 4.4 Vp-p
Signal-noise ratio: 110 dB
Bandwidth: 100 Hz
Offset: 8 uV
Common-mode rejection ratio: 140 db
Gain accuracy: 0.6 %
Chip area: 0.8 mm2
Power: 505 uW
Figure of merit = snr + 10 log (bw/p): 163 dB
 

 

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