Imager for UHD
February 23, 2015, ISSCC, San Francisco, Ryohei Funatsu from NHK Science and Technology Research Laboratories described a 133 M pixel, 60 fps CMOS image sensor for use in the coming 8k TV systems. This next-generation system is expected to start test broadcast services next year, with initial 8k rollout starting in 2018, to iron out all the issues before the 2020 Tokyo Olympics.
The current specifications for the 8k systems are 7680 X 4320 resolution at 120 or 60 Hz frame frequency with a bit depth of 10 or 12 bits. All of these specifications are likely to change as full systems start being used. Current 8k cameras use either three 33M (R,B,G) sensors with 4300 TV line resolution for large studio-type cameras or small single sensor Bayer CFA with 3600 TV lines resolution in a hand-held format factor.
This design with 133 M pixels can provide high resolution in a small form factor by using 66 M pixels for dual green sensors, and 33 M pixels for both red and blue. The sensor can operate at 60 FPS in a progressive format with a 12-bit depth. The demonstration chip is manufactured in a 180 nm process with 2.45 X 2.45 micron pixels in an active area of 37.6 X 21.2 mm.
The sensor feeds 154388 analog channels to a 32:1 multiplexer and then to 484 SAR ADCs. The digital outputs go to 112 channels with 1.15 Gb/s bandwidth per channel for a total output bandwidth of 128.7 Gb/s. the chip is arranged as a rectangle of pixel arrays with readout and ADC circuitry above and below the sensors. Timing control and row drivers are on the left and right sides of the pixel array.
The conversion rate of the redundant successive approximation register ADC is 17.95 Ms/s. The differential 14-bit converters have a radix 1.85 redundancy to relax the reference voltage settling time, and the 12-bit effective resolution is achieved with a 14-12-bit decoder.
The critical issues for large sensors of this type are the ADC reference and power supply distribution and the SAR control logic signal distribution. This design uses smaller blocks of 30 ADCs and logic to provide more local control to get around the distribution issues. The timing is managed with PLL and a clock generator (local gunlock) at each sub-block.
The digital readout blocks use SRAM and 16 CML output ports, with SRAM1 for ADC outputs and SRAM2 for buffers. The 14-bit data are 2:1 serialized into 7-bit DDR data and go to the CML differential buffer ports. Each output port has 9 CML pairs, 7 for data and 2 for control and clock.
The demonstration device uses FPGAs for master clock and timing generation, and for output signal processing. The circuit exhibits many spikes with some greater than 6 LSB. The spikes depend on clock rate and sensor driver circuitry. Total power is about 11 W with more than half going to the digital portion. The imager captures a fairly clean color image with resolution over 4000 TV lines.
