Power Optimizations in the Gen 9 Graphics
August 19, 2015, Intel Developer Forum, San Francisco—Jason Ross described the design, architecture, and processing changes that enabled improved performance at lower power for the graphics engines in the latest Intel core processors. The changes reflect the changing environments for the commercial-grade parts.
In the past, PCs and their graphics engines had the luxury of large boxes that could handle big heat sinks and virtually unlimited power for the machine. Now, the shrinking form factors are resulting in smaller, lighter, and power-limited housings that don’t have much capacity for cooling. Despite these changes, users have increasing expectations for performance and would like all-day operation on a battery. The latest platforms are being used for computational and graphics intensive functions like AR, media analytics, and computational photography. The challenge is to support lower power, greater performance, and more pixels in a mobile power profile.
The main components for power consumption are dynamic and leakage. Dynamic power is a function of capacitance, frequency and voltage squared. A voltage-frequency plot for power shows an inflection point where power starts increasing much faster than frequency. This inflection point is the optimal operating point for the design and process. The best ways to take advantage of this point is to use multiple cores, greater parallelism, and scalable architectures. Changing to a smaller process node allows new tradeoffs in the use of the faster devices for higher performance at higher leakage, or slower devices with lower leakage. The smaller devices also permit the system architect to make fine-grained changes in the architecture to optimize the tradeoffs in parallelism and complexity.
The latest iCore processors take advantage of architectural and processing changes by moving to a 14 nm process and changing the architecture of the graphics processing units. The GPU now has two main processing blocks, the unslice, and the slice. The unslice does pipeline control and other front-end functions while the slice has both fixed function and programmable sections.
A single slice has 24 execution units and three shader samplers in addition to the fixed function sections. The slice can handle 8 pixels per clock. Another version of processor called a GT3 has a second slice and media fixed functions, and the GT4 has three slices. This family allows the user to work with different graphics subsections to allow choices in power and performance.
This architecture allows the use of split and multiple clock and voltage domains to manage power. Power gating is very fine grained, down to single execution units. The unslice unit has automatic strip detection and creation features to detect redundant vertices and eliminate overlaps during render. As a result, the render engines are working at close to 1 vertex per triangle per cycle. This tessellation greatly reduces the number of points to process.
The GPU also uses a lossless render target compression scheme to minimize data transfers, and can pass data directly to the display. The GPU works in 16-bit floating point, which is over twice as fast as an equivalent 32-bit operand. All of these changes help to reduce the power. One version of the chip can deliver high-end graphics within a 4.5 W budget. The overall SoC has reduced power in the CPU cores and now looks like a memory-side embedded DRAM to the rest of the system, eliminating data transfers to and from memory, further reducing power requirements.
