New Technology will require 10x reduction in power
February 21, 2011, ISSCC, San Francisco–The plenary session ended with a roundtable discussion entitled ” Beyond the Horizon: The Next 10X Reduction I Power- challenges and Solutions”. The panel looked at the challenges and changes needed to achieve a order of magnitude reduction in power consumption.
Jan Rabaey from UC Berkeley moderated the discussion, assisted by domain experts Hugo De Man from Imec in Belgium, Mark Horowitz from Stanford, and Takayasu Sakurai from the University of Tokyo. The panelists were Jack Sun from TSMC, Dan Dobberpuhl a consultant, Kiyoo Itoh from Hitachi, Philippe Magarshack from STMicroelectroinics, Asad Adibi from UCLA, and Hermann Eul from Infineon Technologies.
Rabaey framed the topic by noting that Gene Frantz observed that DSP energy efficiency improves every 18 months, but must keep scaling to continue to progress in performance and circuit density. The challenge is that technology scaling is having a diminishing input into increases in density and performance. Voltage scaling is limited by leakage and process variability and noise and reliability are also contributing factors.
To continue the energy improvements, we have to minimize waste. The majority of IC designs now use the full range of energy efficiency design techniques but are barely keeping up with the need for greater energy reductions. At this time, there are no “game changing” devices in sight. So where will this 10X come from?
TSMC’s Sun advocated a bottoms-up focus on technology. He compared and contrasted the human brain and ICs. He noted that the brain consumed about 20W of energy in 100B neurons, or about 1 trillion transistor equivalents. The brain is a very 3D structure with extremely high fan-in and fan out per node. A high-performance CPU on the other hand consumes about 200W in 3 billion transistors. An IC is essentially a 2D structure with an average fan-in and fan-out of 5.
As a result, we must consider density as a driver for performance and must move to much higher parallelism. This change will reduce the energy for performance, but it requires the design start with a full evaluation of system and architectures consisting of heterogeneous multi-core and high parallelism.
CMOS has always been chasing speed and device density at a constant power density. Now they are reducing voltage even lower and still trying to get high bandwidth. Digital functions are becoming more analog and analog functions are becoming more important to digital operations. The next generation will be looking at “green” interconnect with lower resistance and extremely low interlayer dielectrics. Other possible changes include more new materials and device topology options to enable super swing and very low voltage operation. Other possibilities are junction-less transistors and high mobility III-V materials.
Dobberpuhl noted that power efficiency has always been a function of performance per watt. Classical process scaling provided a k-3 improvement, but it is now approaching a 1/k value. The easy circuit changes have already been done and the aggressive power management scaling, such as clock and power gating, multiple and variable thresholds, and others are wringing out as much wasted power as possible.
CAD can still work on individual cells to optimize for energy efficiency while the place and route functions can become more energy aware in their algorithms. A bigger influence is in changing architectures to be much more parallel and improving algorithms to be power aware. We will have to continue to scale voltage, where we still get a fairly large improvement for a relatively small change.
We need to find a solution for SRAM at very low Vdd and improve threshold controls to reduce mismatch. At the same time, we need to improve device dynamic range. One way to get there is to change from 6T to 8T SRAM cell. The 8T cells have better noise margin and better operating range. Threshold voltage distributions are a problem, since the current distributions have a high leakage tail that makes device leakage a bigger problem. Power distribution is dominated by changes in threshold voltage and delay is highly affected by the sigma of the threshold voltage.
CAD and the internal circuits need to have statistical evaluation capabilities to address the variability of the latest processes. These circuits need dynamic error detection and correction. Analog circuits need to become adaptive and digitally assisted. The architectures have to go towards higher parallelism hardware, possibly with integrated FPGA for accelerating functions.
Hitachi’s Itoh addressed the challenges in memory. The first issue is the variability of the devices, the second is low voltage logic, and the third is the conversion of memory from 6T to 8T cells. The fully depleted SOI process technology has a number of possible implementations. One is to continue the planar structures, which have the advantage of back bias for dual supplies and thresholds. The other is FINFET which has much lower variability in thresholds but no back bias.
Ideally, we will solve all of the issues at once and have FD-SOI and repair for low voltage SRAM and logic. At present, 1 GB of RAM draws about 10 A with the supply at 1 V and threshold voltage of 0.25 V. By increasing the Vt to 0.37 V and reducing the supply to 0.5 V, the power can be reduced to 2W.
ST’s Magarshack opined that designers need to look at more variables when developing new designs. They must look at time versus the operating environment versus the specifications. Often, there are changing power patterns over time. The operating temperature also changes versus time. Over a longer operating time interval, the internal devices also change.
So far, most designs suffer from over design and excessive margins. The practice of divide and conquer forces allocation of margin to all of the design teams. Therefore, a change in design philosophy could be a solution for 10x. If the designers developed specifications that followed the requirements rather than always in worst case, significant reductions are possible. Not all functions require maximum performance.
In the future, all levels of the design will negotiate their operating specifications with their neighbors. For example global clocks could be replaced by globally asynchronous clocks for specific clock domains. At the extreme, all circuitry could be asynchronous. In the next generations of 3D processes, heterogeneous subsystems would optimize performance by sensing and reacting to local and global conditions. The system has to interact with the internal circuits and the circuits have to interact with the process.
Designs will go to very wide I/O and wireless communications will use smart antennas. Various CMOS processes can be mixed with stacking technologies like TSV and FDSOI transistors will help to reduce leakage. The challenge is to develop a design flow and tools to handle 3D and mixed processes and to develop the models necessary to analyze this blend.
Future design flows will have to be aware of the applications, packaging, power management, real-time responses, variability, device aging models and all of these parameters need to be optimized simultaneously. In addition, the designs will have to have integrated sensing of the environment to adapt to changing conditions. Models will have to address all aspects of the system to only use energy when it is needed. All of these design aspects need better tools and models to be successful.
UCLA’s Adibi noted that wireless will be a key feature in many systems. A radical change in receiver topologies is necessary to address the dichotomy of low noise and highly linear operation. The current practice of using an active FET with high gm and high ft results in high currents. If the input transistor is changed to one operating in a passive mode with minimal ft , the resulting zero bias device results in a low resistance, low noise input stage. This low noise baseband does not need to operate in a 50 ? environment.
In transmitters, the tradeoff has been between high efficiency and linearity. By changing the output to a class D structure with a fast FET switch, the power amplifier efficiency increased and can drive the output structures directly. This requires the FET to operate at fairly high voltage, so a GaN on silicon transistor with a dual phase drive would work well. The RF oscillator efficiency is proportional to the inverse of the inductance. Good oscillators need low-loss, high Q inductors so the designer can use an external packaged inductor that is connected via bumps.
For even more energy reduction, low power protocols are much more effective than circuit changes. The system has to take advantage of power-down modes in the RF stages as well as in the other sections. Adaptive transmitters and receivers can change bandwidth based on noise or data rates
Infineon’s Eul stated that GSM is migrating to LTE which offers 200 X the power efficiency and 10,000 times the data rates. Existing chips are about 30 percent analog and 70 percent digital. In the future, with changes in algorithms and architectures, the analog will be much more like the digital portions. Designers still need to reduce the number of transistors in their designs.
One example is to use a digital transmitter. The design changes from I and Q signals going to a D/A converter to a low pass filter, to a mixer to an adder and then to the power amplifier to a I and Q signals going to a cordic which develops magnitude and phase signals feeding to filters which then go to mixer, adder and power amplifier. This architecture eliminates the D/A converter and reduces operating power by 50 percent. It also takes less space. Changing power efficiency enables changes in communications technologies. The software defined radio and integrated mixed-signal functions enable power and cost savings.
Stanford’s Horowitz asked how common technologies and architectures allow for differentiation and how low supply voltages could go. Dobberpuhl responded that variability is an issue. Adaptive supply control adds margin to the parametric controller, a technique that has been demonstrated in some applications. Companies have a range of opportunities for every design even if they are using common hardwired IP. The problem is one of validation, not imagination.
Sakurai queried how to establish cooperation across the system functions. He also wondered how to design and control threshold voltages and their variability. Sun suggested that designers always want the best structure for the lowest variability. A FinFET has lower mismatch than a planar one, about 1 mV per micron at 0.5 V Vdd. The ability to scale threshold voltages depends upon process control, so design has to cover for process failures. Itoh contended that new MOSFET structures like FDSOI and FinFETs still offer tradeoffs. Planar devices are cheaper to manufacture and can use the bulk materials for back bias, but Fin devices have much lower variability,so there is no single answer.
deMan inquired about power reductions due to software changes. He noted that software activity varies in memory and other areas. Hardware is always better because it is more ?? Eul responded that the system could compute local activity through local sensors. Changes to the circuitry and operating conditions could allow for lower operating frequencies. Flexibility is always better in software than in hardware.
Horowitz posed the question on power reduction in the radio components and how the extra control circuitry might increase standby energy consumption. Adibi answered that there is a relationship between flexibility and overhead to implement that flexibility. By moving to a flexible architecture, you avoid the limits of a fixed structure. Hardware acceleration enables the software radio, which is necessary to realize reduced power.
Sakurai looked for more information on the R & D for new memory elements like R/M/ and PCRAM. Itoh considered them attractive as a change to existing memory hierarchies. They all can reduce the size of the memory subsystems. All of the new technologies need to scale down to sizes compatible with the latest processes. There are issues with write endurance and the costs of the additional processing. One alternative is to change SRAM to DRAM, which greatly reduces standby power. The newest designs have much longer retention, so battery back- up is one possibility.
deMan noted that complexity keeps increasing. Is there a growing separation of concerns so EDA companies can pay for R & D for new tools and still get a ROI or will new tool development move in-house for the large manufacturers. Magarshack replied tha EDA is about a $5 B industry, compared to the video game industry at $15 B. the tools enable Moore’s Law to continue and will be available for the 14, 10 and 7 nm nodes. To use all of the transistor available in these technologies will require a holistic design style and a lot of design effort. Academia contributes to the research. The big vendor shall have some good tools and there are always new start-ups.
Magarshack continued that the next generation designs will need close cooperation from users, EDA, and the fabs. The current 32/28 nm generation shows the possibilities fo this type of 3-way partnership. Collaboration and progress need standards that give parameters for partnerships, as in the RTL-SystemC-TLM transitions.
Finally, Rabeay asked for the one biggest factor for energy reduction in the future. Sun suggested transistor basics and statistics. Dobberpuhl offered voltage, Itoh opined variability control, Magarshack responded sensors and reactivity on FDSOI. Abidi considered radical changes and Eul tendered architecture.
