Emerging Challenges in NAND Flash Technology
August 10, 2011, flash memory summit, Santa Clara, CA—Seaung Suk Lee from Hynix talked about the need for low cost, high reliability NAND to enable solutions in storage. The increase in bit density has impacted flash endurance and data retention, adding to the challenges facing flash development.
First, some market statistics. This year, flash is expected to sell about $25 billion in product, increasing to $30 billion by ’14. Mobile, tablets, and SSDs account for 44 percent of the total market, growing to 50 percent next year and 68 percent in 2014. The cost per bit is steadily decreasing, aided by increases in bit density. High performance and high reliability are possible with a good controller, and more standard interfaces are becoming available.
Continuing to increase the density is going to be very difficult. Linear scaling through photolithography processes has now moved to double patterning to get feature resolution. The challenges for very small scale devices are electrical interference, capacitive coupling and dielectric leakage. As a result, there are very large implementation issues affecting further linear scaling.
In addition to the implementation issues scaling, programming speed is becoming a problem. The interconnect materials for the word lines are moving towards air gaps to reduce signal loading. The gates stack itself needs significant engineering to find materials which minimize leakage when working with 10 to 100 electrons. The process needs a high-k dielectric for scaling, but high-k materials are unstable.
To operate the small devices requires a read window margin at the 1X nanometer node that enables some separation between read levels. This reduction in margin will need stronger ECC to detect and correct errors, or aggressive signal processing to enhance read reliability. A partial solution to increasing bit density is to stack die and an integrated controller into the flash packaging.
A promising alternative is to make gates stacks in other non-planar structures. These 3-D structures enable vertical stacking of bits and can achieve much higher bid densities without going to smaller process nodes. Such structures need deep etch and polysilicon polish capabilities, as well as some form of dual control gate. The advantages of moving in this direction are higher reliability and performance coupled with greatly relaxed design rules. For even greater bit density, two wafers can be bonded together in a hybrid 3-D structure. The industry is moving to solve the issues of next-generation silicon structures that resulted in reduced product cost coupled with increased yield and reliability.
