Enova Security Conversion Chips

 August 2011 – In a recent discussion with Robert Wann, CEO of Enova Technology had a chance to review their new offering in the storage hardware encryption chipset line the X-Wall MX 256 and the X-Wall MX 256C. Enova is known for its FIPS level certified interface chips that make the basis of many of the self-encrypting rotating disk drives from Seagate, Rocstor and others.

The company’s prior product, the X-Wall DX is a USB 2.0 self-encrypting chip. It modifies the data going into a USB storage device that is compliant with USB 1.0, 1.1 or 2.0 interfaces. This encryption was then brought to the IDE world in 2000 with a full productline around in-line data self encryption with AES ranging from AES-64 to AES-256C. The controller translation supports ATA to ATA (X-Wall-CO, X-Wall-LX and X-Wall-XO products). The newer products are the SATA to SATA chipset (X-Wall-MX) and USB2.0-to-SATA (X-Wall-FX). The USB to SATA devices is targeted at externally connected SSDs.

ENOVA SATA to SATA Encryption Chip flow

The chipsets are fairly scalable in their application scope, the MX product not only supports both AES ECB anc AES CBC encryption (128/192 and 256 bit) but can be parallelized to 16 wide to support 16 NAS devices or 16 individual drives from a single centralized key management and certificate. These chips feature power down control, support for Linux and x86 applications and have a pre-boot password authentication software routine as part of the BIOS code for the device. The SATA implementation is currently 3Gb/s (SATA II), and a higher performances version of the chipset will be available when market demands drives it.

The current version can perform crypto at >150MB/sec, supports >2TB hard drives, only draws 219mA @ 1.8v, and 12mA @ 3.3V for power over the extended temperature range of -45 to +90C. The MX parts are FIPS 140-2 Level 3 certified (Cert #1471) and have been adopted by both commercial and US Govt agencies. The chipset is supported by a centralize key management platform that works with a pair of Secure Key key tokens. The tokens are managed in such a way that the distribution is randomized and duplicate tokens cannot be issued.

This chipset is available now, and is targeted to bring security to existing systems by placing the chip in the data stream to the storage devices whether it be a USB, SATA or PATA interface, and now providing FIPS level security to existing non-secured devices.

PC