PCI-SIG Announces Roadmap

September 12, 2012, Intel Developer Forum, San Francisco—We talked with Al Yanes from the PCI-SIG about the latest developments for this interface specification. The Peripheral Component Interface is a common I/O interface in many computers and servers.

PCIe 3.0 was released in ’10 with 8 G transfers per second data rates and many other optimizations as an upgrade to the 2.0 specs. The framework for 4.0 was announced last year and is expected to be ratified by early ’15. This next generation interface will double the data rate and will allow new form factors for emerging market segments. Another consideration is to reduce the power for PCIe operations.

One of the primary applications for PCIe is for storage peripherals, and the organization is working to address the needs of this segment. The 3.0 spec is optimized for high throughput and low latency for storage, especially with SSDs. The 4.0 spec is looking forward to the needs of the next generation storage systems to increase bandwidth and reduce costs by increasing clock rates to reduce I/O pin count for the same data rates.

One new set of challenges is that some of the higher data rates will require new form factor and cabling. The PCIe Oculink cable will enable 8 Gbps with head room to expand to higher rates over time. The links will be in copper or optical forms with an independent reference clock. The links will support up to 4 PCI lanes at 8Gbps in each direction. This cable spec is expected to show up in products in late ’13 or early ’14.

One weak point is that the new NVMe spec uses the PCIe electrical and mechanical specifications, but the group is not a member of PCI-SIG. This spec is focused on high-performance storage as a replacement for the serial attached SCSI (SAS) or serial ATA (SATA) devices.

Other form factors in consideration now include the next generation form factor for the ultra light and thin platforms. These will replace the mini- and half mini-card formats with a smaller package. The smaller forms will enable better scalability with support for WiFi, SSD, and WWAN. The final specification is expected t be released in Q1 of ’13.

In light of the power issues, they are looking into technologies for tablet type platforms. The L-1 link sub-state will extend the 3.0 spec will optimize idle power and permit longer operation on batteries. In addition, the organization is working with the MIPI Alliance to deliver a protocol that operates over the MIPI M-PHY layer. This will extend the PCIe architecture to mobile and handheld devices. Implementers will have to be a member in both PCI-SIG and MIPI. The ECN for the 3.0 spec will be delivered later this year, with point release in late ’13. The final spec will be included in the 4.0 release.

As always, the next generation PCI will be fully back compatible with current and past hardware and software interfaces. For more information, see www.pcisig.com