BEARS New Directions in Provably-Optimal Implementations
February 14, 2013, EECS, University of California, Berkeley—The annual EECS status update focused on cloud and computer-based functions, and the need for optimization in all aspects of computing. The ASPIRE project (Algorithms and Specializers for Provably-optimal Implementations with Resiliency and Efficiency) is looking at extensions to their parallel computing work.
Krste Asanovic is looking at future apps in areas like augmented reality, robots, speech interfaces and recognition, sound, and big data. All of these apps require lots of compute power, and future metrics for performance will include power and energy efficiency. One glaring need is to improve energy efficiency in computations.
Moore’s law and Dennard’s theories on scaling are hitting a wall. Supplies are getting stuck at about 1 V due to the needs for vt to be high enough to gain performance. But now the high vt needed for speed are causing leakage to skyrocket. In addition, the fine-line processes are increasing the device variability as we move to more parallelism.
PARLAB was focused on how to parallel program, and assumed the hardware would be there. The move to parallel cores is only a one-time gain, unlike lithographic scaling which has been going on for the past 50 years. As a result, designers will have to move to simpler cores or extremely low Vdd and lower frequencies to maintain the device increases.
One can only make a core so small, then you lose any additional advantages. One response has been to use more dark silicon, sections are turned off when not used, saving significant power. The result is that many SoCs are now locally synchronous and globally asynchronous. Specialized accelerators can be turned on and off as needed, and the whole system can have heterogeneous compute engines that are scaled for the tasks at hand. A specialized accelerator can be 100 to 1,000 times more efficient than a general-purpose CPU.
The problem is that hardware and software cost something. The real issue is that communications at all levels—on-chip, cross-chip, off-chip, and throughout the system—cost energy. One task is to identify the limits and drive the algorithms and architectures to those limits through provably optimal implementations and communications-avoiding algorithms.
In the past, all of the focus was on flops and developing processor models. For example, to improve run-time and energy use requires considerations of dynamic energy, state variables, the energy cost of holding data, and background energy use. If you can prove a lower bound for processor and memory, you can get a linear speed up at a constant energy. Other algorithms may be more efficient.
Communications avoidance leads to systems that approach the lower bounds. Developing and implementing these data models calls for optimizing the software stack and the processors to reduce the communications. Programming an apps processor comprised of a central core and specialized subsystems is a challenge. the ensemble specialized processor can be flexible or fast. Commonality and patterns will have to be mapped to each engine.
All apps have some standard functions, so a hardware engine for each function is feasible. The programming model calls for higher levels of abstraction to find and use the patterns and compile to specific engines. The apps processors also need some programmable fabric to help the agile hardware development and for rapid configuration. The computer engines will be in a state of constant iterations.
To program these new processors calls for a new language. They developed SCALA for hardware modeling and description. In parallel, they have a new hardware description language called Chisel. Resilient electronics and modeling can trade off MTBF and energy per fab. ASPIRE is working on hardware and software design tools to address the newest challenges.
