Next Generation Lithography
February 18, 2013, ISSCC, San Francisco—Martin van den Brink from ASML talked about the next generation lithography and the challenges ahead. For the industry to continue its push on decreasing costs and increased functionality, scaling needs to continue.
The challenges in scaling are to get more productivity and yield and the same or lower cost. Current methods call for improvements in immersion lithography and double patterning. To truly move on, we need to find disruptive and more highly scalable technologies such as EUV and 450 mm wafers.
The industry is moving towards sub-10nm resolution, with 14nm coming on-line soon. So far, double patterning is working for the current processes, and it may be possible to extend multi-patterning below 14nm. Cost is the major issue for the sub-20nm processors, as early information shows that the cost for a million gates is higher for 14nm than for 28nm. The cost for a single transistor is not going down as in previous generations, but is hitting a saturation point.
The lithography roadmaps support the industry targets for cost per gate, but depend upon getting EUV into production. The 193nm sources cannot meet the cost reduction targets, and neither can the EUV at 60 wafers per hour. The industry target of a 70% cost reduction per node needs EUV to get over 125 wafers per hour to be viable.
As the processes go to FinFET or FDSOI, the desired cost reductions are not apparent, and in fact may even be going up faster than the density improvements. If we stay on the ArF laser sources to the 14 nm node, we will have to play catch up on the costs and might be even by the 7nm node. At the same time, we may be watching the transition to 450 mm wafers by the time we get to the 7nm node.
Immersion will be the workhorse technology through 2020, and developments in triple and quadruple patterning may keep the production costs close to those desired. current equipment can achieve a throughput of over 200 wafers per hour, and increasing throughput to 250 is within view. EUV is projected to come on line by 2015, but there are a lot of physics and engineering issues that need to be resolved before that can happen. The current throughput is over 60 wafers per hour, but that needs to double to be viable.
The move to 450mm is also projected to take place about 2015, so the production savings may come from larger wafers, rather than lithography. All things being equal, a larger wafer increases die per wafer without increasing production costs per wafer. The production will have to use conventional lithography, computational lithography, overlays, and CD metrology and feedback loops to extend the processes to smaller dimensions in the larger wafers.
If the throughput at 450 mm is increased from the current 125 wafers per hour to 250-300 wafers per hour, you are well above cost neutral performance. The non-lighographic savings can make up for a lot of other problems with the technologies.
The semiconductor roadmaps all call for further scaling. The 20-22 nm node is in production. the 16-14 nm node is scheduled for next year and will use FinFETs or FDSOI with RMG-HKMG processes. Base material will continue to be silicon. The 10nm node is projected to start in ’16, continuing with the silicon-based technologies. By the 7 nm node, we will have to have nanowires in a III-V graphene base by ’18 or later.
With significant layout restrictions, we can see cost efficient 1-D scaling with immersion to 10nm half pitch for NAND Flash and processors. The process will be very complex, requiring source and mask optimization, and sidewall assisted multiple patterning. The challenges in getting a 2-D scale factor calls for triple patterning at the 14nm node. While it is possible to consider continued work on immersion overlay down to 3nm, the industry needs EUV.
Logic can only scale to 10nm with EUV. The layout restrictions and triple patterning will not allow more than a 25 percent shrink, and features will be marginal at that time. The process window needs to be wider to increase the resolution budget. The lack of good CD control and the need for enlarged overlap process windows means that the 193nm DUV exposure source is unable to keep up with the demands.
The challenges for EUV are not easily overcome. A lack of a pellicle ( a covering to protect the mask from particles ) and the issue of mask defects means that micron-sized particles in immersion become nanometer-sized particles in EUV. With a pellicle, the defect tolerances increases, but you need 90 percent transmission across a 114 x 142 mm reticule.
Source issues include source lifetimes and output power. Current power output is about 40W, with 60W in view. For a 60W generator with 4 x 10 9 pulses represents about 100 wafers per hour in potential throughput. The ideal is to get a 70W source and 70 wafers per hour by 14nm. This output can be extended to 7nm with optimized illumination. The economics don’t work out well at this level.
Look to see dual mode 300/450 production equipment using immersion. The 450mm equipment is doable but the lithography costs are an issue. The industry is investing in the R&D for this equipment to speed up the developments. Full cross over to 450 mm wafers is likely by ’18.
The future depends upon both 450mm and EUV to continue to scale die sizes and costs over time. The lithography challenges can hold back scaling and performance, but the issues are not insurmountable. The disruptive changes will occur when the directed self-assemble techniques become production ready.
