Tilera – bringing compute closer to I/O
February 2013 – At the RSA conference, Tilera was showing their 3rd generation programmable product the GX72. This is a 72 tile core that is an addition to the existing GX36 36 core array. The GX36 is a staple of the high throughput community providing 40G I/Os next to high performance computing and access to a PCIe Gen 2 interface. The chip can be placed on a single slot card, including heat sink and only draws 30W of power for a CPU that has the compute capability equal to a Sandybridge processor.
The Tilera array unlike an FPGA, is software programmable using C and the configuration is reprogrammable in application. This makes the array a component of choice for VOD and QAM vendors in the streaming video space. The current design is used in stock trading applications as a custom processor, due to the access to high speed I/Os and low latency, even for UDP applications, in the 1.7us range for turnaround. The programmable compute supports the implementation of encode and decoder blocks for H.264 for video conference applications including audio processing and multi-screen transcoding.
The GX36, which is shipping, is architected to minimize I/O congestion, by providing 8 lanes of PCIe Gen 2 at a 99% duty cycle. This can deliver a max of 32Gbps which is reality is a functional 28Gbps. On the other side of the I/O, is programmable crypto blocks supporting AES encryption with optional cores use for decrypt. As these data networks address more and larger data, higher speed hardware is needed. The GX72, which is sampling in Q1 ’13 and production Q4 ’13, will double the capability of the current solutions, reducing the turnaround latency due to the 40nm process technology, and with 72 cores and 4 embedded memory controllers, it should support 100G PCIe Gen2 throughput.
