IMEC Research Overview
July 8, 2013, IMEC Technology Forum, San Francisco—Luc van den Hove from IMEC described the overriding philosophies and some of the results of their research in his opening talk at the forum. The general concept for their work is the sum of minds.
IMEC tries to bring together a wide range of diverse and complementary skills for their research. Their experience over time has shown that most changes and discoveries are at the boundaries of disciplines and in cross pollination across fields. Here are a few examples to demonstrate the efficacy of this process.
A cell sorter on a chip is used in cancer detection where researchers are trying to detect one cancerous cell in a billion other cells. Existing systems are large, slow, and mostly manual. A lab on a chip uses 30 micron channels to separate different cell types for analysis. The ASIC for this analysis has over a thousand channels for this work, increasing throughput and accuracy.
This development required expertise in CMOS design and manufacturing, life scientists, imaging, MEMS, hardware and software integration, and prototyping and fabrication. No single expert could have completed this work. In a similar manner, other bio-and medical functions are getting attention, with improved diagnostics, treatments, and research are the eventual outcomes.
Of course, at Semicon, one must talk about process developments. Their research is 2-3 generations ahead of the industry and is now focused on 7 and 5 nm devices. In the past, scaling was mostly geometric, but, since the turn of the century, has become a physics, materials, and device architecture problem. The newest processes all use mobility enhancement materials engineering and now research is in replacing the Si channels with Ge or III-V materials.
As the topologies change to vertical constructions, other materials for the substrate, like graphene, are being considered for logic and memories. Memories are getting their share of materials engineering efforts, and new memory structures like MRAM are under investigation.
At the same time, we will need to improve our ability to make 3-D packages. This technology enables heterogeneous processes in a system-level chip. The challenges are in tools to evaluate new architectures as a part of the overall design process. The changing applications will allow designers to create many alternative and assess those options for the most viable solution and identify directions of most likely failures to avoid.
All of the process issues will need follow on characterization and metrology, as packaging modeling and simulation help to predict performance, functionality, and reliability. Materials engineering will become more important as the high-mobility materials become more highly integrated into the overall process flows. Here, also, new tools and flows are needed to characterize and model the technologies. TCAD, reliability, and lithographic compatibility will become even more important when total error budgets are a small fraction of a nanometer.
The lithography will eventually have to change from 193 nm to something else. EUV is slowly making progress with new 0.33 N.A. optics, but the challenges of output power, availability, and source lifetimes have to be overcome. The alternative of directed self assembly is likely to be a complement to the base EUV processing flow. The overriding issue is whether the new processes can achieve a halving of the cost per gate.
The costs issues first became dominant, partially due to the introduction of multiple patterning. At 14 nm, highly restricted design rules will become a part of process, system, and circuit design, and will require starting with an architecture that is 3-D aware. At the systems level, even a 3-D package is insufficient to meet the demands for I/O, so systems will have to include silicon photonics.
To meet the demands for research, IMEC has a full 300 mm pilot line with advanced immersion scanners and all the other tools needed to investigate new processes as well as modifications to existing processes. In addition to looking at 450 mm wafers as alternatives to EUV, they are building more infrastructure with their partners to demonstrate the full ecosystem needed for development and evaluation.
Finally, they are working on large, high-resolution, high-contrast flexible AMOLED displays. These devices represent the most likely directions for next-generation displays on flexible substrates. Their work includes modeling, simulation, reliability, large-area electronics, packaging, characterization and metrology, and low power design. The challenges are to find materials and processes that are low temperature, prevent oxidization, and can manage the stretching and alignment of the substrates.
These are not all of their research projects, but a sampling of the types of issues they address, and a demonstration of the need for multi-disciplinary approaches needed to solve the next-generation challenges.
