Chip Design After Moore’s Law Ends

August 26, 2013, Hot Chips Conference, Stanford, CA—Robert Colwell, director of the Microsystems technology office at DARPA and former Intel manager, sees the end of Dennard scaling within the next decade, resulting in Moore’s Law becoming a purely economic function. The coming end of Moore’s Law is something that the industry looks at like watching “Peter Pan” and really, really believing that we can make Tinkerbell well.

The semiconductor industry has made a fantastic run from discretes to SoCs to meet the growing expectations for better performance. The improvements in the industry have enabled greater separation of concerns, leading to many specialists like design, layout, etc. The evolution of CMOS, which doesn’t have any viable replacements yet, and the tools for design have encouraged this separation.

The issue now is that Moore really expressed the continuous movements of optimal points on curves and the economics are significant factors. Unfortunately, all exponentials come to an end. For Moore’s Law, this should happen in about 2020 and at the 7nm process node. At that time, the volume, yield, profit, and costs for fabs with new process development will diverge and end the exponential.

Until now, the silicon has provided free improvements for designers. The chips have increased performance by a factor of over 3500, with architectures have contributed about 50X imrpovement since the early ’80’s. The increased performance comes from faster clocks, which allow more logical steps to be handled in the same time. These easy improvements have already seen a plateau, as clock frequencies stopped increasing at the same rate in the late ’90’s.

The lower limit to more improvements is about 10 percent, at which point, the costs of design and process development no longer justify the next process node. It is possible to continue to ramp up performance at a Moore rate for a short time, but there are very few tricks left to exploit. The unfortunate reality is that no one can forecast the future of technology.

DARPA is looking at some alternatives to silicon improvements as a part of their technology evaluation process. 3-D stacking is certainly going to increase circuit density and offers some performance improvements, but requires major changes in architectures and known-good die manufacturing technologies. Cooling and much higher battery capacities can help for a while.

Big changes in software, micro-architectures, architectures, I/O. and memory can offer performance benefits until they catch up with the silicon. Then these “soft” areas will also hit the wall. New applications and operating modes will be useful to the users and will give the impression of better performance. At some threshold, resilience will provide to be useful, but the value of that change may be swamped by the increased die costs.

One very good possibility is in finding a new switch. There are a lot of investigations into new materials like carbon nanotubes, graphene, and even more exotic compounds. Some MEMS are candidates for very low power latches and logic, but need a lot of work to become manufacturable. Better system features like sensors, wireless, displays, and the human interface can mask other deficiencies in the system, and at some level of performance, can be seen as sufficient. One area to consider is marketing! Someone will try to sell the lack of performance improvement as a benefit in other areas, like “green” or cost efficient.

Our dependence on CMOS is a problem. We take the assumptions about CMOS logic as givens, even though they have become illusions for a long time. Now designers must consider issues like transmission lines, high-frequency design, and other indignities that used to be just parasitics, as design constraints and the problems just keep getting worse. Meta-stability and thermal issues make the design work harder, and we must end this separation of concerns because all of the issues are interrelated.

The power limits for the chips makes the increased use of specialized hardware for better performance necessary for the next 2-3 orders of magnitude of changes. Some of the possible hardware includes dedicated blocks, approximate computing, and analog computing. The approximate compute takes advantage of the fact that most of the time, we don’t need a high-precision answer, but close enough. Analog compute can be a part of the approximate implementation.

Future designers need to master chips and “neighboring technologies” to absorb more of the value proposition. A lesson from “Intel Inside” is to get the buyer to relate perceived value to your part of the final product. Apple iTunes made getting music easy, and the white earbuds made it fashionable to listen to your music. The new designer needs expertise beyond the chip and CPU to include communications, biology, physics and materials, control theory and related stability issues, and other things that no one has thought of yet.

The communications will encompass everything; RF, networks, fiber, etc. so the designer needs to know more about the end applications. The communications theory, signals, noise, modulation techniques, propagation, and even regulations become a part of the design. One challenge is that all information is probabilistic with some error rate. The challenge is to make the communications more resilient, much more like the telephone system than our computers.

Designers should also pay attention to the adjacent sciences of physics and biology. Physics and materials will need advances in photonics, lasers, and infrared. The physics of some of the newer materials like phase-change will require more innovation as will the advanced MEMS. And something will come from physics that will follow CMOS. Electronics at the meso and atomic scale will be where the post-Moore designs will emerge.

In the biological areas, electronics can offer interesting approaches to areas like genetics and human anatomy. The field of engineered biologicals will need techniques like synthesis to move forward. And most importantly, brain and human interfaces will need both the physics and biology constructs to make new interfaces possible. The whole system will include the human as a functional component.

When Moore’s Law ends, it will be economics that stops it, and not the physics. Flagship machine design may end when the potential for scaling for greater profits no longer exists. The costs of next generation design, processing, and tooling will become cost prohibitive and make the next generation machine economically infeasible.

The alternatives are to consider more special purpose designs, but these functions must be programmable to avoid the problems of past specialty circuits. The benefits of scaling are reaching diminishing returns and the process doesn’t matter, because everything will eventually reach an end point. The semiconductor sweet spot does not ignore the economics. Leading-edge technologies benefit from shrinking, but the payoff matters.

DARPA has a program called Upside, that is looking at alternative compute methods. Analog is one of the candidates, but like other prospects does not have some program controlling the computer process. The approximate computer will use the minimum number of bits needed. Low energy, probabilistic compute will use component like spin torque oscillators to drive the system to a minimal energy state.

The extent of the changes means that the post-Moore computers will not be back-compatible with today’s machines. The different levels of abstraction and interface modes will make compatibility very difficult. Once again, the issue is how to make money. The higher up people will need to understand the implications of the new architectures.

Some of the outcomes for the end of Moore are that the viable older processes will become commodity platforms and all electronics will have DRAM-type margins. Cars have gained from Moore’ Law, so the car manufacturers will start to really suffer when the “free” performance and cost improvements end.