Suvolta Reduces ARM Cortex Power

August 26, 2013, Hot Chips Conference, Stanford, CA-David Kidd from Suvota presented an ARM Cortex implementation that reduced power by half, using deeply depleted channel transistors. Although the ARM core is not a power hog, the implications for the other functions in an SoC are significant.

In a deeply depleted channel transistor, the basic FET channel structure is modified to put an undoped or lightly doped region next to the gate, supported by a moderately doped region, on top of a highly doped region on the bottom. This structure provides better matching, higher analog gain, multiple Vt on chip, and a strong body coefficient. The strong body coefficient pulls in the corner distributions into the typical range with body bias. Modifying the body bias also helps to reduce active and leakage power.

A demonstration project used the DCC devices in an ARM Cortex -M0 CPU. The demonstration was in a 55nm process with silicon gates. Experiments show that the body bias needs to be calculated relative to process monitor devices for best effect. Applying a target bias to the whole chip corrects the performance of all devices to within 13 percent of the target performance, and the leakage of the fast corners is reduced to that of the typical devices.

The resulting design reduced the dynamic and leakage power compared to the fast corner by half, and provided a relative match between the fast and slow corner performance. In terms of performance, the design can trade equivalent performance at half the power for a 35 percent performance boost at the same power, or a 55 percent increase in performance at the same operating voltage.

The implementation added less than 1 percent overhead for the bias network with very relaxed design rules. They made all routing in columns, double spaced the bias wires for reliability, and used separate wires for PMOS and NMOS devices. The DDC transistors also reduced the minimum voltage for the SRAMS by 150 mV at 125°C with a bias voltage of -0.6 V, which also increases the yield. SRAM retention power also dropped with less than half the leakage in standby and retention modes in a 65 nm process.

The technology is also useable in the advanced technology nodes with metal gate processes at 28nm and 22nm for all types of designs. The modular implementation allows for gradual replacement into the various types of designs, including logic, analog, and SRAM.

The devices can be used in a mode to trade off lower leakage for lower performance or improving performance at matched Vdd. The rationale for changing to a DDC is that the high-performance devices have a lower threshold, which increases leakage. The performance transistors contribute a disproportionate amount of leakage, over 60 percent of the chip total, for the less than 2 percent of the circuitry that need the high-performance devices. A power analysis shows that a DDC transistor operating at 125° C gets improved leakage characteristics when body bias is added.