Hot chips – high-performance computing
August 20, 2010—Hot Chips Conference—Stanford, CA. Olav Lindtjorn from Schlumberger talked about “surviving the end of scaling of traditional computers in high-performance computing”. Current computer configurations have run into memory and power walls. An alternative to larger server farms for high-performance computing is to develop a data flow configuration within an FPGA as is outlined in the example presented at the conference.
In the field of oil and gas exploration, the main consideration is identifying resources modes of access in order to maximize recovery. To do this, they use a number of sources for their data including acoustic, electro-magnetic, and gravity sensors. In a normal configuration, they use thousands of sensors arranged in linear arrays. In marine environments these arrays may be as long as 6 miles.
The sensor arrays measure intensity and physical characteristic information that generate tremendous amounts of data requiring very high computational requirements. The typical array might have 25,000 sensors which can generate 2 GB of data at a 30 Hz data rate per measurement instance. To properly map the field, they might run 200,000 shots of data collection generating about 200 TB of data. Altogether these operations might take 5 to 7 days.
To get finer resolution on the topology, requires increasing the data recovery bandwidth from 30 Hz to 60 Hz. This increases the data volume by a square factor and also increases the imaging complexity by 80 percent of their efforts going into identifying additional resources, 15 percent to identify the modes of access, and the remaining 5 percent looking at maximizing recovery.
The physics involved in the data analysis require convolution and sparse matrix operations. By putting dedicated FPGAs into the data flow, they are able to add 1 million processing elements to the 96 GB of DRAM to feed data to the storage arrays. The design software has help them manage bandwidth allocation and data flow limits. This hybrid structure also improves overall scalability, since CPU-based simulations saturate at 5 to 8 processors. The FPGA array gives them a 40 times increase in throughput.
The 3-D convolutions they are computing generate very large data sets. The FPGA provides hundreds pipeline stages and four megabits of bulk RAM which enables time step cascading through dedicated functional units. These functional units are fixed point because floating-point is not needed. The increased resolution of a floating-point unit creates a very large performance penalty.
The alternative of using GPU’s, with more mature products, existing ecosystems, and large development communities helps since GPU’s are much faster than CPUs for data processing. However, FPGAs can be designed with dedicated functions which are much faster than a programmable unit. They’re working with some domain specific languages from Stanford with platforms for developing FPGAs.
