Novel Dynamics in a Consolidating Semiconductor Landscape

July 7, 2014, IMEC Technology Forum, San Francisco—An Steegen from IMEC described the requirements and readiness of next-generation processes for semiconductors. The production of semiconductors beyond 14nm is going to challenge our existing design and manufacturing flows and will take new devices and technologies to replace out CMOS infrastructure.

The general industry directions are for more information moving to smart and connected devices. The oncoming IoT raises security issues, while all of the other challenges of power and data rates are still around. The core CMOS technology has to address the power, area, and cost triads and the processes continue their plunge into deeper complexity.

The lithography for the next generations will have to conform to the requirements for computational corrections, double patterning, and other limits. Printing the logic transistors in the sub-20nm processes will get much harder. For the 7nm node, the dimensions for features like gates and fins drive the minimum dimensions, while the metal pitch will run at 2-3X minimal dimensions.

Multi-patterning will require some type of restricted design rules as the design flow includes evaluation of 3-D process steps. The advanced patterning solutions will call for overlays of multiple pattern segments raising resolution and alignment issues. The lithography scaling roadmap suggests that the contacted poly pitch at the 5nm node will require EUV, with resolution below 3nm. This line width will need high numerical aperture EUV for illumination.

Another challenge is the number of masks needed for the future process generations. Going from 20nm to 7nm increases the number of masks from 27 to unkown levels. The advent of EUV reverses this trend and reduces the total mask set to eight (8) 193 i-line and six (6) EUV masks. The EUV tools have the necessary resolution for this level of work, and early work suggests that the resists are almost there.

EUV mask issues include the need for structures to be multi-layer and the ability to detect errors and particles. The particle issue is important since the EUV masks do not have a pellicle to minimize particle defects. The possibility of particle defects on the backside of the mask and the defect height of those particles is another concern. An alternative to the standard lithography might be directed self assembly (DSA). This technology has some design tool issues, as the design for DSA must account for problems like hole propagation, material purity, and the overall integration scheme.

CMOS has always been trading power and performance. In the past, voltage scaling helped the power, but has met its limits. Now electro-static functions like leakage are becoming dominant. The performance depends upon drive current, carrier mobility, and RC loading. The future efforts will have to focus on reducing variability across all of these parameters for reliable and consistent performance. The active devices will need better control of depletion and the fully depleted SOI and FinFETs are going to a gate all around type of structure to provide better current control within the devices.

At the very small dimensions, the performance of Fin versus nano-wires and the corresponding consideration of Fin height versus gate length will dictate performance limits. At 7nm, 3 nano-wires are equivalent to the performance of a FinFET. The controlling factor is the gate-contact spacing, and one work-around is to make the nano-wires vertical. This change gives a 20-30 percent area reduction and lower leakage due to the relaxed gate length. The difficulty will be in integrating these devices into a production flow.

Other performance enhancements will be more source-drain stressors, but this technique cannot scale to sub-1 nm. as a result, the changes will be in the channel modes. they foresee a 80+ percent Ge channel for the P-type devices and an InGaAs channel for the N-types. This channel engineering with alternate materials gives the equivalent of a process node improvement in performance. Ge and the other III-V materials will also allow the Vdd to go from 0.8 to 0.5V which will help the power consumption. There are still many unresolved issues with the III-V N-type channels before they can be considered for full production.

Beyond CMOS, early investigations are in 2-D nano-lattices, tunneling devices, spin transistors, and even piezo-mechanical devices for switches. Examples of some 2-D materials include MoS2/SiO2/Si stacks. These materials have good performance in terms of current, but have some mobility issues and need a low-temperature back-end-of-line process. Eutectic magnetics may be useful in majority gate structures, and magnetic tunnel junction devices may be acceptable in slow, low-power functions.

The BEOL processing will have to address the RC problems and improve reliability. Integrated processing with self-aligned contacts will reduce resistivity and ease the overlay budget. The 10nm and smaller nodes will need triple pattering if EUV is not available in the 2016 timeframe, and new techniques for contact and via fill will be bottom-up with other metals like Co or W. At the 7nm node, we might see air gaps in the interlayer dielectric materials and a change in design styles to a 1-D metal 1.

In memories, extensive work in going on to find replacements for SRAM and Flash. One requirements is a change in memory hierarchies and classes. Systems have to go from high-speed, high-power and low-speed, high-volume architectures to a storage-class set of devices. Candidates include CBRAM, PCM, ST-MRAM for this type of storage. Flash will become a 3-D structure with laser thermal anneal for the gate materials.

Chip interfaces will have to meet the requirements of greater than 1 TB/s bandwidth at a power of less than 1 pJ /bit. One way to meet these requirements is to go to a stacked die approach and reduce loading by interconnecting devices through TSVs. The basic technologies for wafer thinning to less than 2 microns are already available. The issues for further refinement are in stack quality and the integration and various models: thermal, thermal/mechanical, interface, and reliability. The various types of 3-D SoC include system in package, stacked die with an interposer, and front-to-front bonded wafers.

I/O challenges also must consider package-package loading and even go to rack-rack communications. In-package optical and silicon photonics are a possibility if the many challenges can be overcome. Optical interconnects offer great power efficiency and the characteristics of wavelength division multiplexing and other techniques will allow many signals to share a single conduit. The roadmap for semiconductors is changing to signal the end of CMOS as the workhorse process.