IBM envisions 3-D integration
December 8, 2010, 3-D Architectures for Semiconductor Integration and Packaging conference, Burlingame, CA—the first talk on 3-D directions came from IBM. Subramanian Iyer, fellow from IBM who discussed ” 3D Integration for High Performance System Applications”.
Despite advances in scaling, materials, and silicon engineering, the IC performance levels are not improving at historical rates. Now, SoCs are facing new limits on power and thermal management, so performance has to come from changes in internal configurations. One way to improve performance is to improve data locality by adding or increasing caches.
The problems with increasing the number and size of caches are die area and power dissipation. The SRAM for L1, 2,and 3 caches is now exceeding 50 percent of the die area and power consumption. The trend towards multi-core architectures makes the design and integration even harder when some of the memories are shared. To address the area and power budgets, they developed a DRAM that has 3-3.5x better density that the SRAM while reducing standby current over 5x .
The zEnterprise 196 processor has 4 core areas each with 64 KB I-cache, 128 KB D-cache, 1.5 MB L2 cache. The whole array has an additional 24 MB of shared L3 cache plus controllers and interfaces. A companion chip holds an additional 96 MB of L4 cache plus controller and multiple 40 GB/s inter-chip interfaces to other processors in the system.
The 3D implementation of the chipset requires an interconnect methodology, a joining technique, thermal management in an equivalent to origami in silicon. The system-in-package approach works for low power processor die, but cannot address the thermal issues and power issues. The high performance processors are running 150-200 W and need to have about 200 A uniformly distributed to the die and power grid.
To get the most out of a 3D stack, designers have to trade off between a hierarchy of interconnect types. Die-to-die interconnect is handled by bumps on face-to-face die, and is best suited for I/O and power, and unit interconnects. TSV is for macro and circuit interconnect. The higher the TSV density, the greater the possible 3D integration. If the TSVs are in the first for metal layers, there is a higher integration difficulty. But if the vias are at the last metal, the on-chip wireability is much lower.
One benefit of TSV is the ability to integrate decoupling caps into the structure. The large surface area of a TSV permits high value caps to be designed as a part of the interconnect structure in the power connections. This capability locally decouples mid-frequency noise without using processor real estate. In addition, the noise reduction improves performance by about 10 percent.
