Progress in 3-D IC production
December 9, 2010, 3-D Architectures for Semiconductor Integration and Packaging conference, Burlingame, CA— Bob Patti, CTO at Tezzaron Semiconductor illustrated the changes in complexity when changing from wafer-level to 3-D integration.
The span of interconnect densities goes from 100 to 1 million connections per square mm and may total from 1000's to tens of millions. Their current products stack DRAM and a controller chip using a tungsten via first TSV that is 0.85 u square and 10 u deep. After completing the balance of metallization in copper, two wafers are bonded face-to-face. Then the top wafer is thinned to 5.5 u to expose the TSVs, lapped and metalized with aluminum. Next, a third wafer is bonded to the stack face to back to give two DRAM layers. Finally, the whole wafer assembly is flipped, thinned and padded out. Overall, they are producing 30 million TSVs on an 8-inch wafer.
As a part of their research into future levels of integration, they are using DARPA Multi-project wafers and doing up to 5 layers of circuitry. This MPW becomes a silicon workbench, which is used to develop 2-D to 3-D building blocks for other uses. The existing PDK for a 130 nm process is working fine for their current work, since a three-layer TSV stack two generations back can attain the same circuit density as the latest process node.
By using a via first approach to insert tungsten vias at metal 4 in a near end of line process, the TSV processing is now possible at any fab. Challenges are in CAD, partitioning, and 3-D P&R. To do their physical designs and checking , they use the MicroMagic physical editor for its incremental GDS scan capabilities. Magma has a tools that performs a 2.5-D LVS, and all other tools are standard. 3-D integration which needs independent tech files per layer. The problems are that they need standard formats for the layers, since some layers are upside down there are challenges. Data and storage is a bigger issue than for a individual SoC, because they need 3 full wafers worth of data for one 3-D design.
The driver and rationale for 3-D is the need for a 50x increase in memory density without the corresponding increase in the number of pins for the memory array. By splitting up the die into separate functions allows them to increase memory size, speed, while reducing power versus using more of the SoC area for eDRAM. The main application for 3-D memories in the near future will be for power and DDR termination. Going 3-D leaves room for expansion, as extra pads are available for more connections.
In the future, they will have logic on memory plus up to 1 uF in bypass capacitors integrated into via areas. They need standards for die-level information and foundry interfaces due to lots of little issues when moving to production. They also need more manufacturing information, especially on the low-K interlayer dielectrics to move to newer processes. Test is through IEEE 1149 and 1500 and shows little from single wafers. The process yield is about 90 percent with most losses from edge die. They do not see any additional thermal issues in the stack because the basic limit is still about 1 W per square mm, whether in 2-D or 3-D.