Applied Materials discusses equipment for 3-D IC integration

 December 9, 2010, 3-D Architectures for Semiconductor Integration and Packaging conference, Burlingame, CA—Hans Stork, group vice president and CTO at Applied Materials described the technology landscape for TSVs and the drivers and applications that will use these connections.

The baselines for the different unit processes and their integration into a manufacturing flow for TSV last middle, backside contact, and interposer depend on interactions of many elements. This interaction eventually will lead to cost effective solutions for high through-put production, but will require collaboration across the entire industry ecosystem.

The areas that need a lot of development include bonding, adhesives, de-bonding, wafer thinning, TCAD, and metrology. Some consortia are developing to work on the issues to bring the technologies to manufacturing. These groups are looking at various unit processes including etch recipes for via middle, via last, silicon recess, and via last oxide open. The entire via process needs refinement starting with dielectric liners, PVD barrier/seed source development.

Details for step coverage and titanium barriers as well as bottom-up, low over-burden fill, to achieve small post-anneal protrusions will contribute to better CMP. Ideally, this will be a low temperature (<180 C) process to minimize disruptions to circuit parameters. The etch constraints have multiple solutions but total co-optimization will depend upon the overall flow.

As the unit processes are brought on-line, the process integration requires better understanding of the baselines for interposers, via middle, and via last to achieve the range of aspect ratios and backside reveal. The step coverage and high aspect ratios of the vias plus the facts that these connections are very large areas of metal increases materials and processing costs.

The bonded wafers processing—adhesive, bonding, thinning, and wafer edge management—requires more technical collaboration. The TSV etch requirements for uniformity and undercut under the metals, coupled with the extreme thinness of the silicon and glass to manage the aspect rations, increases the challenges.

Test and inspection flows are in development with the goal of minimizing the these jobs in production. Simulation and characterization of production, defects, capacitance, and stress can lead to cost of ownership benchmarking and metrics for continuous process improvement. The issue is that dimensions vary and the mechanical dimensions matter to the final product.

The processes need to be integrated into a repeatable flow so all products and processes are in sync and the various parameters can be traded off for best yields. Manufacturers need to understand the processing effects on electrical parameters and reliability. Identifying the process recipe requires complete knowledge of all the conflicting requirements. All of the various unit processes will need some customization to manage and optimize the flow for different applications and to feedback information to other parts of the flow.

The equipment for the various process steps is already available or is in late stages of development. Much of the equipment is just enhancements to existing products for processes like via etch, plasma and chemical vapor deposition, and chemical-mechanical polishing. All of the tools work together in current manufacturing, so the only new processes like wafer thinning and temporary bonding and de-bonding will need external collaboration for production tools. By looking at adjacent unit processes, collaborators can maximize their learning curve.