Litho for 15nm nanoelectronics – SFBAC IEEE Nano Council

 November 16, 2010, Santa Clara, CA—SFBA Nanotechnology Council held a symposium on “Nanoelectronics: Innovation and Implementation” at the National Semiconductor conference center. Chris Bencher, distinguished technical staff at Applied Materials talked about “Process and Integration-Based Scaling for 15 nm Nodes” in the opening session.

First, he reviewed the progression of technologies for lithography. In the ’80’s the exposing light was smaller than the feature size, so shadow projection worked fine. By the ’90’s, feature size and wavelength were about equal. Now, the wavelength is much larger than the feature size and requires a change to a diffraction-dominated era.

The features are scaling much faster than the lithography, which causes great difficulties in developing new processes. To address the challenges, a number of new technologies are put in place. First, the masks are now highly modified with many reticle enhancing technologies including optical proximity correction and phase shift masks, so the source pattern has very little relation to the intended design. In addition, the illumination sources are point or planar sources, but are moving off-axis.

Second, the optics companies are working to increase the numerical aperture. The resolution is determined by K1 = feature X N.A./?. At the 250 ? node, K1 values were 1.0. At the 65 nm node, K1 is 0.3 and needs to go even lower for the next generation processes. Early experiments in off-axis illumination indicate that it is possible to optimize the illumination source by designing a light pattern to interact with the model-based OPC to enhance the sub-resolution resist features. This co-optimization of light and masks has been working in some RAM designs. One challenge in advancing this technology is the lower levels of regularity of normal circuits and the corresponding difficulties in metrology and QA.

Third, design for manufacturing tools are now an accepted requirement. The result of the increasing use of DFM tools is the movement towards more regular layouts. By minimizing jogs and T shaped junctions on all metals, the design becomes more manufacturable. This layout simplification helps the patterning by making layouts one dimensional, you only care about line lengths and spaces. The dimensional reduction makes the imaging scanner resolution limits less severe. The optical components are capable of going to a K1 of 0.27 by using immersion techniques, which takes the optical technologies to down to 40 nm.

Double patterning, the fourth area, gets you to 20 nm, since you get one half pitch per pattern. Some 32 nm and 28 nm NAND flash is in production using double patterning, indicating positive results down to 20 nm. Some 1.35 N.A. ArF lasers are moving into high volume production and have a native half-pitch of 40 nm. With sidewall spacer double patterning (SSDP), this resolution goes to 20 nm. The hope for EUV exposure technologies will bring about a theoretical resolution of 15 nm is easily capable of native 25 nm resolution.

SSDP is a complex manufacturing technique that starts from minimum spacing images for spaces and double spacing for lines. The materials are processed, resulting in minimal spaced lines and spaces. A hard sidewall is grown on the sides and over the top of the line features. A minimal space is defined on the line, which becomes a sacrificial mandrill, and the space is defined and etched. The resulting structure is a set of minimal lines and spaces with the lines defined by a sidewall and an etched wall.

To get below 20 nm, will require something more than just double patterning. If NAND flash stays on its current node progression rate, the industry will need a 15 nm half-pitch resolution by 2014. If logic adopts 3d devices such as finFETs, the industry will see 15 nm resolution in late ’14 or ’15. The options for 15 nm production are:

ArF light in a dry exposure giving 120 nm resolution and requiring quad patterning. This uses a double-double exposure and production flow and is available today. The challenges are in CD control and tolerance build-up. This option is operationally difficult due to the number of patterning steps and the 30 percent line width roughness. Although this is the most mature technology, it needs full CD evaluations at all stages of manufacturing to ensure required accuracy.

ArF immersion is good to 90 nm and gets to 15 with SS triple patterning. This process is a spacer-based triple pattern process that keeps the mandrill.

EUV gives 60 nm which enables a SSDP to give 15nm for a half pitch. Measured results on a small sample give a CD uniformity of 0.61 and spacers of 1.97 nm. Line width resolution tolerance is 1.5 nm for the lines and 2.5 nm for the spaces. This technology uses the existing infrastructure of design and manufacturing tools. The only real problem is throughput which is extremely low compared to existing solutions.

ArF dry with self assembly quad patterning is possible using polystyrene or PMMA. The self-assembly depends upon the short range order of the materials. So far, they have been able to make lines and spaces, but need improved epi materials to allow lines to turn into circuits. Early results are at least 6-9 months out.

Nano wires are still a long way off, as the polymer work shows. We can handle polymers by so far, but don’t know how to grow and assemble functionalized nanowires.

Direct e-beam exposure is becoming very interesting. The great value to the manufacturers is no masks. New systems are being created with thousands of beams and multiple writes to activate the resists, this technology offers the possibility for high volume throughput and acceptable numbers of imaging errors.