TSMC sub 28nm CMOS – SFBAC IEEE Nano Council
November 16, 2010, Santa Clara, CA—SFBA Nanotechnology Council held a symposium on “Nanoelectronics: Innovation and Implementation” where Di Ma, vice president of applications and technology at TSMC talked about the “Technology Challenges in 28 nm CMOS and Beyond”. The general premise was that Moore’s law is going to continue, until advanced technology nodes no longer provide increased performance, density, and reduced power per device.
The challenges for the latest nodes require a complete ecosystem to address the many impediments to design completion. A design team must have access to design IP and a wide range of tools, while the manufacturing groups need advanced processing equipment and materials suppliers. All technology requires increased investments from all parties involved in the design and manufacture of those designs.
As an example of the successes possible from this level of cooperation, the 40 nm node, a 1/3 node shrink from 45 nm, now has 45 customers with over 250 design projects. Over 130 have already taped out and 70 percent of those are in full production. At the current rates, this production will amount to over 500,000 -300 mm wafers by the end of the year.
The trends for scaling are still holding true. Their latest RAM cell is still on the shrinkage curve and expectations, for at least the next generation, show continuing success in shrinking RAM area. Performance continues to increase, while power per switch drops. An additional benefit of the latest generation of processes is lower leakage.
In the past, shrinks were based on increased speed on a constant leakage. Now power per area is the constant. The tradeoff between power and speed has changed so instead of striving for a 30 percent increase in performance at a 40 percent decrease in power for the next node, they are working towards a 15 percent increase in performance at a 60 percent decrease in power.
At the 28 nm node, they have elected to use a gate-last approach which results in increased performance, lower Vt, and stronger PMOS devices. The reduced Vt allows an even lower Vdd which contributes to lower total power dissipation. The manufacturing process has shown better Vt stability and reduced process induced defects. Because the gates are processed after all of the high temperature steps, they are seeing higher reliability due to fully protection of the high k gate dielectric materials.
They anticipate that further scaling is possible for this manufacturing flow and better control of the individual device parameters associated with the dual work functions for the metal gates. At the 28 nm node they see larger interactions with the device parameters, so the rationale for the changes in CMOS to HfO2 N+/P+ metal gate self-aligned surface channel devices holds the best promise for further scaling.
The 28 nm node will have two versions of hi-k metal gate and silicon oxynitride. It is getting robust yields. So far, TSMC has invested almost $6 B in capacity, mostly for the 40 nm process. At present, the ramp for 28nm looks to be faster than was for 40 nm.
On their roadmap for next generation processes, the big issues are in lithography. They are looking at better immersion tools and new layout splits. Future work is needed in EUV and e-beam systems to get the desired throughput. Research continues on high mobility channel materials and manufacturing processes. At the same time, they are looking into the next generation of high –k metal gate structures as well as non-planar topologies. Variability and reducing RC delays continues to be high on the list of important to-dos.
For their lithography, they are getting their first EUV equipment deliveries next year. Current issues are the capital and operating costs of the new equipment. Throughput is expected to be in the 60 wafer per hour range and the many masks are both expensive and will require frequent set ups and recalibration. No matter what they do, costs will increase, because each piece of equipment will get more use for the same level of wafer output.
The work on multiple beam e-beam equipment is interesting. With 110 beams at 5 kV they are showing good CD uniformity. By scaling this equipment to 13,000 beams, they could expect about 10 wafers per hour. Clustering a number of these machines could result in something approaching their target of 100 wafers per hour.
To do all of this R&D costs a lot of money. They are spending 16 times the amount they spent developing the 0.25 ? node. Now they are developing the second generation of high-k metal gate devices and are on their 4th or 5th generation of stress enhancement. Other work goes on in Ge channels and finFETs where they are achieving 1708 ?A/micron saturation currents. In addition to all of the silicon device work, they are also working on packaging and 3-D ICs. Their work on TSV and silicon interposers is showing good manufacturing results.
