HSA releases new specification
May 2016 – The Heterogeneous System Architecture (HSA) Foundation released an update to their system specification and finalized version 1.1. The focus on the update to the specification is the definition of the interfaces that enable interoperability between IP blocks from different vendors that compose an HSA system. This specification is the first in the industry to define the interfaces for a multi-vendor architecture support solution rather than a single supplier solution. While applicable at traditional systems, the V1.1 specification is targeted at SOC providers.
HSA Platform Overview
In order to address the multi-vendor IP implementations, the new development environment supports multiple languages. The virtual machine that is the core of the HSA system is created through an abstraction process from code written in OpenCL, Python, C++ Amp, C++ V17, OpenCL2 and OpenMP. Currently, these code blocks write directly to the device and IP block with a direct data store for those modules. The new release places the updated HSAIL interface to handle the distribution in the coherent memory configuration. The HSAIL interface is a RISC based load store with inherent parallelism that drives the finalizer. The finalizer directs the compiler to target the code to the correct device in the architecture so it can be optimally be executed on the CPU, GPU or custom DSP.
HSA software overview
The use of the new compiler and the finalizer has the system architecture and the coherent memory configuration using all user mode calls, so there is no longer a need for interrupts or I/O based calls. The new specification also defines optimizations that include control of non-temporal memory access allowing infrequently used values to be removed from a cache efficiently.
Other improvements that made their way into the new specification include run-time enhancements including the capability to wait on multiple signals and new heterogeneous system-level profiling capabilities with support for an architected event/timestamp model and performance evaluation enabling users to access hardware information for profile guided optimizations or analysis. The V1.1 release is the first to include a formal definition of the memory model for the RAM and Cache coherent systems.
