EDA view on 3-D ICs
December 8, 2010, 3-D Architectures for Semiconductor Integration and Packaging conference, Burlingame, CA—Anton Domic senior vice president at Synopsys started out noting that > 2D integration is already here in the form of stacked die and package on package technologies. There are a number of products in production using these technologies.
3-D IC integration is slowly moving towards production, but the drivers differ for each application. For stacked memories like NAND flash with densities greater than 64 Gb, the driver is cost. The homogeneity of the dice permits a small number of TSVs in a single array and fairly small total keep out zones (KOZ). For multi-core processors with more than 16 cores, the driver is speed, since the memory bus is 2-3x slower than the CPUs. Again, the chip regularity allows for a small number of TSVs and KOZ.
For SoCs, 3-D depends on an architecture that has well identifiable and self-contained or self sufficient sub-systems. The pros and cons are unique for each SoC. This level of integration allows the mixing of optimized analog and digital sections at the cost of a medium of large number of TSVs. Ideally, this structure permits heterogeneous, multi-foundry stacking of functions, but needs standards to become realistic.
One area where 3-D could make a big difference is in stacked transistors on a chip. By optimizing the NMOS devices on one layer and the PMOS devices on another layer a designer could achieve better performance and lower power when the layers are connected with TSVs. The problem is that this structure requires a huge number of TSVs to work .
3-D integration looks great from a process standpoint. The performance available from a 2D node N is ~= to a node N-2 in 3-D. This permits much easier Digital and A&MS integration, a smaller footprint, shorter global interconnect, better timing and lower power. The problem, however, is that the costs may outweigh the benefits. Wafers will cost about 5 percent more than standard wafers. The area and power savings depend heavily upon the number of TSVs and their placement while the reduced area means less room for the bumps. Yield will be lower than a single IC and device variations will require device binning and some form of known or at least suspected good die. To cap the issue, there are no tools, flows, and methodologies available for the 3-D integration.
As people consider designing 3-D structures, they have to consider such manufacturing details as via first, middle, or last and determine who in the supply chain does what and at what cost. TSVs create many problems. For a 1um TSV with a 10:1 aspect ratio, the silicon wafer has to be thinned to 10um making wafer handling a serious issue. These TSVs are extremely large compared to device features. At the 32/28 nm node, a TSV is 5-10 times the size of a standard cell height and 15 -30 times the M1 pitch.
The TSVs need to be designed and optimized. The total number of TSVs affects the total chip area and wire length but in different ways. The placement of the TSVs is also critical. A regular, on-grid pattern is sub-optimal, so the layout for a 2D chip would not be good for a 3-D chip. The manufacturing processes like CMP are coupled to stress proximity effects (SPE) and will adversely affect yields and silicon utilization. SPE effects are two orders of magnitude higher than strain engineered functions. This effect requires even larger KOZ and the analog SPE require a KOZ 10 times larger than the digital ones.
Test and assembly become bigger issues in 3-D devices. The designer has to trade off pre-bond testability against power savings. A higher level of test coverage takes more power. Assembly is also impacted. Without some type of binning, some combinations of dice will be out of limits for performance or power.
One alternative to a full change to 3-D is to go to a 2.5-D IC. All of the necessary ingredients are available or are within reach. Passive silicon interposers (SiIP) can deliver 10 times the connectivity compared to dice and package alternatives and 100 times the bandwidth at much lower power. Yields should be on a par with monolithic SoCs and better than a true 3-D stack. In addition, there is no additional thermal burden from a passive layer of interconnect.
Eventually the SiIP could handle all of the global power mesh, simplifying the layer stack or increasing utilization and reducing the die costs at the same time. The system-level I/Os could be moved on to the interposer permitting further die shrinks if the IC is pad limited. Because the interposer is high-grade silicon, active circuitry can be added with little extra cost and sub-systems can be moved into different die, permitting better matching of function and process. All of these changes can enable a full heterogeneous side-by-side and stacked 3-D IC.
