Fast MRAM
February 24, 2015, ISSCC, San Francisco—Hiroki Noguchi from Toshiba highlighted their work on a 3.3 ns embedded STT-MRAM. The design uses a physically eliminated read-disturb scheme and a normally off architecture. Spin-torque transistor magnetic RAM development continues with efforts to overcome some key critical issues.
The growth of last-level cache is helping to overcome the speed gap between processors and DRAM, but the larger caches are now facing a power wall due to leakage. Nevertheless, people are expecting low standby power and faster memory access for the next generation cache memory technology. One change is moving from a single to dual cell and sensing low-resistance parallel states or high-resistance anti-parallel states by reading voltage to achieve a 3.3 ns read.
The ongoing challenges include high power consumption and read disturbance for high-speed reads. Some developed solutions for power include reducing peripheral leakage and reducing active read current by charging the bit lines. Read disturbance is a result of using the same path for read and write, even though the write currents are at lead double the read current.
The resulting design addresses the challenges by changing the read scheme to avoid read disturbance, charge sharing to reduce active read energy, and power gating to cut off peripheral leakage. Read disturb can be suppressed with a short precession and cutting off the cell current until the final read. This current impulse isolates the magnetic junctions during precession and allows for a read-disturb free operating region.
A delayed coupling read scheme reduces capacitive coupling and the separation and isolation of local and global bit lines suppresses invasive read currents. The RC factor becomes another variable in the deign tool kit. Delaying the connections of the global bit lines changes when the RC will increase. As a result, when the sense amplifiers are latching the readout data, all of the bit lines are disconnected.
The delayed coupling enhances precession current and simulations show a two decade improvement in read error rates. The hierarchical bit lines enable faster operation while a bit line equalizer prevents half select disturbances. After the write operation, charge sharing puts the bit lines at half the write voltage to allow potential reuse for the following read rather than discharging the bit lines to zero.
Local and global power gating helps reduce leakage by cutting off power to the peripherals when they are not used. The MRAM is non-volatile, so does not need power to retain data. The fine-grained power gating can power down 32 KB in local arrays, drivers, and sense amps. The 32 K B granularity turns out to be the best for area and latency. Power can be in active, sleep, or deep sleep states with different power domains active. In the active state, all global functions are active, and only the accessed cells are active. In sleep, only the global controller areas are active, and in deep sleep, everything is off. As a result of all the power savings techniques, the leakage goes from 178 uW in all on states to 44.6 uW in sleep, and 80 nW in deep sleep.
