Stacked 3-D Crossbar Resistive Memory
December 15, 2014, IEDM, San Francisco—Sung Hyun Jo from Crossbar presented results of new devices and architectures for resistive RAM. A new selector design improves performance and reduces sneak currents in the memories.
For ultra-high density nonvolatile memory applications (>1Tb), 3D-stackable 1TnR or 1S1R structures is needed. Suppressing the leakage (sneak) current in 1TnR or 1S1R crossbar arrays has been a main challenge for high density RRAM development. Key requirements of selectors include high selectivity (?I @VR, 1/2VR), steep turn on slope, high current density, fast turn on and recovery and high endurance. Alternative devices have been proposed, but most fail the leakage and sneak current requirements.
Previous reported selector devices showed selectivity of 150 ~ 10^5 and turn on slope of 60 ~ 450mV/Dec. This latest crossbar RRAM array uses a Field Assisted Superlinear Threshold (FAST) selector with selectivity of ~10^10, turn on slope < 5mV/dec, and fast turn on and recovery <50ns. A test array of 4Mb 1S1R crossbar shows that the sneak current is suppressed below 0.1nA, while maintaining 10^2 memory on/off ratio and > 10^6 selectivity during cycling, enabling high density memory applications.
The FAST selector utilizes a superlinear threshold layer (STL) in which a conduction path is formed at the threshold electric field. The device provides bidirectional volatile switching with large resistance ratio, high turn on current and steep turn on slope. The measured selectivity for the 100nm x 100nm device is > 10^7, and is limited by the test setup. The switching slope is extremely sharp and is less than 5mV/dec which is beneficial to array level operations for example, larger read voltage margin, and faster read.
The threshold voltages (VTH) of the selector can be tuned by controlling either the STL thickness or device structure. The selector can reliably switch over 100M cycles. For voltage above VTH, the switching speed is faster than 50ns with the on-off transition time less than 5ns. Once a device switches to the on-state, a much smaller hold voltage (VH) is required to deliver a target current IP. VH increases as IP increases, but it was found to be independent of VTH. The small (< 0.3V for 200uA) VH and very large off-state resistance minimize the voltage overhead when integrated with RRAM.
The FAST selectors have been integrated to a passive 4Mb crossbar array and the sneak current has been suppressed below 0.1nA at both 25°C and 125°C. We have also successfully integrated the FAST selectors with RRAM in passive crossbar 1S1R arrays. For large array integration, we developed forming-free low current (? 20uA) RRAM cells to minimize IR drop and power consumption, and selectors with VTH larger than 0.5VPRG but smaller than VPRG of the RRAM to suppress sneak currents during both the program and the read operations.
The integrated 1S1R device shows > 10^2 memory on/off ratio and > 10^6 selectivity The integrated device can reliably switch more than 100K cycles while maintaining the large memory on/off and selectivity.
