3-D Synaptic Architecture for Neuromorphic Computation
December 17 , 2014, IEDM, San Francisco—Tuo-Hung Hou from National Chiao Tung University presented a high-density 3D synaptic architecture based on self-rectifying Ta/TaOx/TiO2/Ti RRAM. The new configurations are potentially useful as energy- and cost-efficient neuromorphic computation hardware.
Existing IT systems based on Si devices and von Neumann architecture suffer from the fundamental problems of device scaling and low energy efficiency. Present neuromorphic computations are implemented using complex Si-based CMOS circuits or software algorithms, and cannot overcome the limitations of low density and high energy consumption. To achieve true human-level artificial intelligence, a low-power two-terminal electronic synapse—a fundamental neuromorphic computation hardware that emulates the functions of a biological synapse—must be developed.
RRAM, sometimes called memristor, is now being actively developed as a low-power electronic synaptic device. It also inspired intriguing applications, such as pattern recognition and auditory processing. RRAM-based synapses exhibit excellent scalability, compact 4F2 cell size, full CMOS compatibility, and ultralow pJ energy consumption per spike, outperforming other electronic synapse candidates.
However, two critical challenges remain. First, high-density 3-D synaptic networks rather than 2-D ones are essential to realize innumerable connections among neurons in the brain. However, a cost-effective 3-D architecture that overcomes the sneak current problem has yet to be developed. Second, reducing the energy consumption to that of a biological synapse (~10 fJ per spike) remains challenging. Recently, a self-rectifying Ta/TaOx/TiO2/Ti cell has shown great potential for implementing 3-D vertical RRAM (V-RRAM) arrays over 10 Mb.
The self-rectifying characteristic enables the first high-density 3-D synaptic architecture using easily fabricated V-RRAM. We also first demonstrate the ultralow energy consumption of less than 10 fJ per spike that represents 100x reduction as compared with the previous best synaptic device [3]. This extremely energy- and cost-efficient high-density 3D synaptic architecture is a breakthrough hardware for future neuromorphic computation.
The device fabrication of the 2D Ta/TaOx (20 nm)/TiO2 (60 nm)/Ti cell with a cell area of 104 µm2. The gradual SET and RESET operations are crucial for analog synaptic devices where the synaptic weight (conductance) is affected by the input (training) strength. The conductance values can be read at -2 V, while very low current with no difference among different states was observed at a positive voltage bias.
Synaptic Functions of alternating potentiating and depressing cycles in the Ta/TaOx/TiO2/Ti device by using consecutive 2000 training pulses. In contrast to the previous filamentary RRAM-based synapse, this device shows monotonically synaptic weight changes with little variation and robust cycling endurance. The potentiating and depressing ability in an identical device allows simultaneous implementation of both excitatory and inhibitory synapses.
In addition, the asymmetric current readout at positive and negative biases provides a high self-rectifying ratio that suppresses sneak current through inactive synapses in the network. Furthermore, the synaptic weight function is tunable using the number of potentiating and depressing pulses. A large number of analog synaptic weight states are known to improve capacity and robustness of neuromorphic systems. An action potential-like waveform was used to emulate STDP in biological synapses. STDP is a critical function for learning and memory in our brains based on the Hebbian learning rule where synaptic weight change depends on the relative timing of pre- and post-synaptic spikes.
Paired-pulse facilitation (PPF) is a short-term synaptic plasticity where reducing time interval between two sequential potentiating pulses enhances synaptic weight. The fitting time constants agree with that of biological synapses. Increasing the number of training pulses (frequent rehearsal) facilitates the transition from short-term memory (STM) to long-term memory (LTM).
The switching and conduction mechanism of the Ta/TaOx/TiO2/Ti cell has been explained elsewhere by oxygen ion migration and homogeneous barrier modulation. The physical equations were used to simulate the SET-controlled and RESET-controlled MLC, alternating potentiating and depressing cycles, and STDP. Furthermore, a compact model of the proposed synaptic device must be developed for future large-scale neuromorphic system design. A set of analytical equations is derived from the physical-based simulation, and thus accurately describe potentiating and depressing characteristics with multiple pulse amplitudes and STDP.
Cost-effective 3-D V-RRAM was fabricated as 3-D synaptic network using a simple process. The double-layer V-RRAM with an effective device area of 0.2 µm2. The 3-D device shows stable potentiating and depressing characteristics and biologically equivalent STDP, similar to those in the 2-D device, but the cell conductance in the area-scaled 3D device is drastically reduced because of the homogeneous current conduction.
Reducing cell conductance is critical for implementing high-density crossbar array and lowering energy consumption per training pulse. The energy consumption can be as low as 7 fJ per training pulse for depression. Although the high input voltage requires further improvement, this result first demonstrates that an electronic synapse can be as energy efficient as a biological one. Both 2-D feature-size scaling and increasing the number of vertically stacked layers would increase integration density in the future. Commercial 3-D vertical NAND technology using a similar fabrication concept is capable of integrating 1011 bits (connections) on a single chip.
