PCI-SIG Updates
June 23, 2015, PCI-SIG Dev-Con, Santa Clara, CA—Al Yanes and Ramin Neshati updated the status of the latest revisions to the PCI specifications. The organization continues to work on low power and alternate form factors for their interface specifications.
The PCI-SIG defines I/O bus specs and form factors with emphasis on compliance and interoperability. The intent is to support cost-effective, high performance, robust interconnects for computers. Currently, there are over 750 world-wide member companies in the organization.
The emergence of IoT is driving the low power initiatives. Enhanced PCIe specifications to reduce power include L1 sub-states to improve power distribution on platforms and lower idle power in sleep mode. Also, they introduced half- and quarter-swing variations for even lower power in the PCIe 4.0 specifications. Half swing has been in the PIC specs from the beginning of PCIe 1.0 and calls for a 400 mW interface. Quarter swing reduces this power by half to 200mW.
To make the PCI architecture available to mobile devices, they have joined with the MIPI alliance to use the M-PHY technology with PCIe. This addition allows the underlying PCI protocol to operate over a low-power PHY, and expands the interface to battery-operated devices. The additional functions allow for flexible lane widths and speeds. The expansions will address the complete range of compute devices and peripherals, from servers and networks, to PCs, storage, and to the mobile spaces.
The mobile spaces call for alternate form factors, since a phone cannot accommodate a standard PCI card. The M.2 and BGA packaging is directed towards the smaller devices, while the SFF-8639 addresses high-density SSDs and the OCuLink enables remote peripherals on optical or copper cables. The OCuLink specifications will define x1, x2, and x4 links with x8 and x16 links coming later. The spec is now at rev. 0.9, with final release for rev. 1.0 in Q3.
The 4.0 spec is now at rev. 0.7 and will provide up to 16 G transfers per second, twice the speed of the current 3.0 devices. Some of the member companies have developed working silicon to handle the specifications, and are ready to release the products to full production in late Q3 or early Q4 of ’16. The higher speeds in version 4.0 will improve big data performance for datacenters with extended accelerators through higher bandwidth and more lanes. A x16 PCIe 4.0 interface could provide 64 GB/s bandwidth for a system.
The entire PCI ecosystem is getting ready for the new specifications, from silicon IP, to verification, protocol debuggers, test equipment, and bridges to other transport protocols like Ethernet. The PCI interface now spans the compete range of compute devices, from servers to smart phones.
