FPGA Accelerators
August 20, 2015, Intel Developer Forum, San Francisco—P.K. Gupta from the Intel Cloud Platform Technology Group advocates using FPGAs for some acceleration tasks. The growing needs for compute and the associated stress on systems requires alternatives to adding more servers, especially in cloud platforms.
The cloud computing services are growing at a CAGR over 15 percent. The challenge facing the cloud providers is to optimize performance and total cost of ownership, meaning that adding more servers is not the best solution. The demands for performance cut across three axes, I/O, CPU, and memory intensive functions.
An FPGA accelerator can provide savings in area and power to bridge the performance gap between software and fixed function hardware. The additional benefit of reconfigurable acceleration enables multiple ( although not simultaneous) hardware functions to take over some software tasks.
These accelerators can perform such tasks as workload optimization, dynamic resource pooling, intelligent resource orchestration, and faster analytics and insights. FPGA-based acceleration takes advantage of programmable hardware at a fraction of the cost of an ASIC and more targeted than a standard product. In addition, many FPGAs can be reprogrammed in system to change functions on the fly.
Intel is shipping a Xeon e5 and FPGA software development platform to help with software development for a CPU-FPGA combination system. The platform includes an Altera Stratix V FPGA. The hardware includes interfaces to PCIe 3.0, DDR3 memory and the CPU. Software features configuration and caching agents, and a memory controller. The software includes accelerator abstraction layer runtime, drivers, and sample applications. FPGA design and configuration tools are available from Altera and other vendors.
The system logical view has the accelerators talking to the processor and main memory through a Quick Path Interconnect (QPI) and a coherent cache to the CPU. The QPI coordinates cache coherency with the processor(s) and performs all the address translation and handshaking for the accelerator. The tool flow calls for partitioning the hardware and software to create a bit-stream for the hardware programming and software that operates within the accelerator abstraction layer.
