Moore’s Law limits? – ISQED 2011
March 15, 2011, ISQED, Santa Clara, CA—Fabian Pease, professor at Stanford talked about “how much longer can Moore’s law hold?” in his keynote talk. The amount of integration is not just the number of transistors and wiring that lithography and processing can put on a piece of silicon.
Historically, integration has always been to reduce costs. The early circuit boards for semiconductors in the ’60’s were wire-wrap and cost about $1 per wire. Printed circuit boards put the wiring on the board and reduced the cost of a connection to under $0.01. In ’69, some thought that 64 bits was the limit of useful integration because the projected yield limits would become prohibitive beyond that level.
The early thoughts on yield issues were based on Poisson distributions with yield being an inverse function of area. By ’70, the first LSI circuits appeared: 4k DRAM, Zilog Z80, and others and they all yielded less than 50 percent, but still much more than projected. The Z80 had 30-40 percent yield until Dr. Ohmi at Tohoku University did careful defect analysis and projected theoretical yield at over 80 percent. The defect distribution was not Poisson. As a result, lithography became the pacing technology for integration limits. In ’77, Moore suggested that design and defects would not be limiting factors for a long time.
With lithography being the key to scaling, the cost of wafer exposure equipment has increased from $100,000 for a ’70’s Perkin Elmer to $50 million for a current ASML machine. But looking at the cost of imaging a minimum feature, the PE machine cost about $2500 per nm, while the ASML machine only costs about $5 per nm. Unfortunately, the costs of the next level are going up, so a minimum nm feature will cost about $10 at the 45 nm node. We are getting stuck because sub-wavelength imaging requires constant phase and amplitude for any image.
One point is easy, the hard part is to make it work for billions of points. RET, immersion, double exposure, double patterning, and other techniques lumped under the design for lithography heading are not keeping up with the physical requirements. The cost of manufacturing is not going down, even with the design for lithography tools. Changing the illumination source is not likely soon.
Current efforts in e-beam lithography are showing that the technology is too slow for high volume manufacturing. The latest e-beam mapper is going to 110 beams, but a production system needs more than 13,000. Challenges include electro-repulsion and beam spreading.
Extreme ultra-violet, a euphemism for soft x-rays, has promise, but is 5 to 10 years away from being in production. EUV is like the Concorde, fast but too expensive to keep in operation. Restricted lithography rules using gratings and regular features are also promising, but we need to find ways to insert patters of cuts into the gratings to be useable.
One new alternative is nano-printing. Mechanical printers have created a double-patterned 13 nm-pitch set of features on a wafer. Ongoing imprint evaluations have shown 2 nm features. This change was based on viewing the issue as a microscope problem and not as a lithography problem. Microscopes use known light and image parameters.
Nevertheless, scaling and increased integration will continue because everything gets better. Power goes down with device size and performance goes up. Unfortunately, interconnect gets worse and total wire length is a function of the size of the chip. One avenue for higher levels of integration is to move to 3-D integration, a disruptive technology.
Integrating above the surface avoids the topological tyranny of transistors in one plane, so the amount of integration goes up. In modern silicon, the active area is less than one part per million of the area, a transistor takes up about 100 x 10 nm. To take advantage of the other dimension requires 3-D enabled CMP and new sets of design and implementation tools.
Moving to the next dimension takes many paths. Existing 3-D technologies include chip stacking and wire bonding, wafer stacking, and even monolithic integration. IBM is mixing monolithic integration with advanced packaging to increase the number of vertical layers per unit area.
Research at Stanford is looking at monolithic stacking of active devices. They can put high quality transistors into any layer. The challenges are to deposit high quality Si on the designer layer. Current methods call for growing Si on the layer then cutting vias into the material. A big challenge is to add the other transistors without using a high temperature step, which affects the bulk transistor parameters.
They can deposit single crystal Si on upper layer of a wafer without high temperature steps by depositing oxide with a LPCVD (low pressure chemical vapor deposition) process and activate the active silicon with a laser anneal step. All these steps are done without a furnace.
As a result, moving to the third dimension continues the trend of electronics over the last 60 years, reducing the costs of interconnect. Given the possibilities for new feature definition technologies and 3-D integration, there are no foreseeable limits in ICs.
