ARM Enables Mobility
August 8, 2011, Hot Chips 23, Stanford, CA—Simon Seegars from ARM described the evolution of ARM processors and how they are now bringing high performance to mobile devices. Technology changes over time and the sometimes the changes bring pleasant surprises to consumers.
Processors and technology have evolved tremendously over the last 30 years. We have gone from luggable computers and brick cell phones to the MacBook Air and smart phones that offer many orders of magnitude better performance at a lower cost, even in current dollars. Connectivity is driving computing and by 2020 will have the Internet of Things (IOT) with sensors everywhere. The PC market will decrease while the handheld market will increase.
There are a number of issues facing this transition, among them security and power consumption. The evolutionary pressures are forcing major increases in functionality coupled with large decreases in prices and form factors, all of this with increasing levels of competition.
Starting in 1990, ARM, a joint development with Acorn Computer, Apple Computer, and VLSI, started work on a new processor architecture. The goal was to create a 32 bit embedded processor which eventually would be used in Apple’s Newton computer. ARM was created to be an IP only company which defined the need to also develop supporting ecosystem for developers.
In 1992, the ARM 7 Thumb was created for cell phone applications and was used in most of the first generation digital phones, also called 2G. The first processors used about 6000 gates on a 3 µ process and measured 7 x 7 mm, the sweet spot for area. Over time, this evolved into today’s smart phones, which are a combination of the Newton plus a cell phone. Now, a Cortex M0 measures 0.07 x 0.07 millimeters.
Forecasts for the next decade are that cell phones, smart phones, and tablets will all be growing markets, even though they all are already big numbers. Phones have evolved in the digital era in a number of phases. First phase at the start of this century were early data phones which could send and receive text messages. Between ‘05 and ‘09, the second phase started with the addition of touchscreens. Since then, the third phase has required tremendous increases in transistors to improve performance to handle full graphics and 3G protocols.
Smart phones are growing in volume, increasing functionality, and emerging functions of tablets to become a super phone for ‘13. These phones will be able to surf the web with full webpages and can act as a replacement for laptop computers. A dock to a keyboard and screen will allow data creation capabilities while apps will enhance consumption. An early example of this phone type is the Motorola Atrix.
The future mobile device will use heterogeneous multiprocessing and the total volume will approach the billion units a year with about $100 worth of computer embedded in the products. The most popular OS will be Android, since iti s an open operating system. These phones will need lots of software for operations, lots of apps for user satisfaction, and connectivity to the Web and cloud for data sources and storage.
The biggest challenge is the fairly limited hardware resources and memory available within the package. Nevertheless, these phones will become the center of most peoples’ world, with apps for everything including e-commerce, entertainment, and social networking. The risk is that security may not keep pace with these developments, and people may have to choose between credit in their wallet or on their phone.
The industry will need to develop trust zones, which require defining a hardware architecture with normal and secure areas, implemented in SOC, and run with a secure OS. The challenges are many. Modern design complexity of a 4G phone is 500 times greater than that for a 2G phone and requires more DSP processing to accelerate functions for power and performance. Implementing chips of this size and complexity will never be easy. Batteries, unfortunately, have improved only about 10 percent per year, which doesn’t even come close to the advances from Moore’s law on the chips.
We definitely will need new batteries to power the next-generation phone. This year the average phone battery is 5.7 W-hours and the average phone consumes about 475 mW in standby mode. Even with advanced low-power processes, overall power consumption for phone is expected to continue to increase for the foreseeable future.
Implementing these chips is an increasingly complex task. Timing signoff alone requires verification across process voltage and temperature corners and these parameters now have over 12 combinations of numbers to work with. On top of the timing issues are the requirements for design for test and manufacturing as well as incorporation of variation modeling into the methodology.
Disaggregation in the industry is changing IDMs to fables users in the IP domain. Fabless company design and distribute their products and get tools from EDA companies and fabs from manufacturers. Now these companies only work in design, use IP and EDA tools, and new marketing. There is very little technical contact between the design and the foundries, which is causing design closure to become a lost art.
Most significantly, the number of companies able to successfully create and implement a processor design is dropping with each process node. There may be five companies who can do this at 22 nm this number may drop to as low as two at 10 nm. The physics issues and the costs of leading edge semiconductor design are getting beyond the resources of most companies.
Process scaling is facing other issues. The costs and time to develop the next generation process have gotten so large, that companies can no longer develop the next generation process by themselves. Process complexity continues to increase. The 40 nm node added strain processing to the silicon, 32 nm added high K to the gates stack, and the 20 nm requires double patterning which leads to double mask costs. 14 nm and anything below that will require EUV but current equipment cannot achieve the necessary throughput. As a result, researchers are looking into other materials as the base for processes below 20nm.
Instead of chasing these increasing costs and complexity, people should change the way they think about their designs, and consider moving towards more multiprocessing. This change requires more effort in power control and new styles of software programming. Stacked die are required to maintain density scaling without changing processes. Designers need to change their concept of design and manufacturing.
To help reduce some of these challenges the latest Cortex part has a coherent interconnect to simplify the software. Coherency issues were first addressed in the A9 version and are limited to a CPU cluster and small software model. The A15 in large saucepan to multiple clusters and by 2015 will be used across the full SOC. A holistic approach to design needs to include architecture, network, software, apps, and many other facets to become a successful solution.
