Automotive Ethernet AVB – Xilinx CES

 January 5, 2011 – San Jose, CA – The automotive products group at Xilinx introduced a new Ethernet Audio/Video Bridge (EAVB) Development Kit co-developed Alliance Program member Digital Design Corp. (DDC) which gives automotive system developers the framework and tools to do large bandwidth data management. Automotive systems are incorporating more video data both in the driving assistance (DA) applications of the car and the infotainment portions in cabin.

New regulation will require backup cameras as standard equipment as early as the 2014 model year, Europe is working on lane change sensor regulation and a number of vehicles already have multi-camera automatic parking systems. The EAVB connection is a lower cost twisted pair copper wire interface that can support 100Mb-1Gbps data rates and is part of the AVNu consortium specification. It brings a number of benefits including – (A) unified timing synchronization for real-time, low latency media and time-sensitive sensor and driving control applications; (B) Reservable bandwidth [up to 75% scheduling per connection] for predicable Quality of Service (QoS) for audio/video traffic; ( C) simultaneous support for media, control content and legacy Ethernet traffic; (D) support for current and legacy protocols such as TCP/IP, UDP, FTP, and HTTP; (E) and it has the Potential to replace MOST® while complementing or partially replacement aspects of FlexRay. This diveristy in application, along with vehicle model specific features, givesthe flexibility of the FPGA a key technology advantage.

The AVB standard has been in place since the first products were launched in 2008 and has been adopted by several automotive OEMs along with promoter, user and integrator BMW. A formal protocol specification under the IEEE 802.1 AS, QAV and QAT standards are in progress. A typical automotive system with different busses running at different data rates and also direct point ro point connection is shown in figure 1.

Xilinx EAVB Application Architecture

The collected data then goes to a central location for diagnostic processing through a DSP and MCU. These were traditionally managed by several ASICs. The FPGA implementation allows for integration the DSP, multi-core and ASIC control logic into a single location including the network interface connections.

The design environment from DDC includes IP for DSP, image processing, ECC and data handing, network administration for the multi-protocol applications and is scalable across the Xiliinx product line. At CES, they will be demoing a Spartan 6 system that had multiple video feeds, infotainment and sensor data streams being managed through a central FPGA device. The development kit is available for design starts now.