20 M Pixel Back-Illuminated Image Sensor
February 23, 2015, ISSCC, San Francisco—Atsushi Suzuki from Sony presented details of a large 20 M pixel image sensor. The goals for the new sensor include low noise, high speed and resolution, and simultaneous video and still outputs.
Some of the key technologies for implementing this design were double column ADC, parallel multiple sampling, data compression, two simultaneous output streams and a stacked imager structure. The double column ADC captures inputs from a 2×2 shared pixel and feeds dual comparators, hybrid counters, and data latches. The outputs can change from low-noise to high-speed or dual stream modes.
In the low-noise mode, the double column ADC reads two vertical signals and each ADC feeds two comparators, two hybrid latches, and tow data latches. The high-speed mode reads four vertical signal lines to the same output structure. The dual stream mode assigns a single vertical line to a ADC and the output goes to single comparator and hybrid counter, but then goes to two data latches.
The parallel multiple sampling takes a single vertical signal and feeds it to two processing chains that are added together. The difference in time between the two lines improves the noise and timing delays by as much as 3 dB at a cost in additional power of 116 mW versus a normal single sample.
A low loss data compression circuit reduces the data stream from a 10 bit to 6 bit representation to reduce the data rate from 19.2 Gbps to 11.5 Gbps. This data rate reduction also reduces the number of 2.3 Gbps lanes required. The reconstruction back to 10 bits still results in more than 60 dB PSNR and undetectable reconstruction artifacts.
The architecture allows for simultaneous output of a 4 M pixel video stream and a 16 M pixel still image, both at a 60 fps rate. The packetized data for the 2×2 sub-pixel video stream goes out on the first two channels, and the full data uses the other 6 lanes. Switches in the data path direct the data from the hybrid counter to the main stream and sub-stream paths.
Putting all of this together required a stacked structure. The back-lighted pixel array in a 90 nm process is placed on top of the 65 nm logic and double column ADC chip. the effective higher level of integration also permits the disparate functions to be on optimal processes, rather than trying to integrate logic, analog conversion, and pixels on the same chip. The final chip set has 12-bit resolution with 3934 vertical and 5256 horizontal pixels. The whole set operates on 532 mW.
