February 2016 – At the Digitial Entertainment World conference in LA, Highwinds was displaying their low latency CDN service that is targeted at OTT, IPTV and mobile content delivery. Several years ago, they entered this competitive marketplace, with a new architecture for their high performance servers that includes advanced storage architecture. The current marketplace is…
February 23, 2015, ISSCC, San Francisco—Sehat Sutardja from Marvell Semiconductor noted that SoC designs are getting too complicated due to the freezing of the underlying computer architectures. The future of design will have to change to allow for more innovation and flexibility for the end products. The costs of SoC mask sets are doubling with…
September 17, 2013, Storage Developer Conference, Santa Clara, CA—Andy Rudoff from Intel talked about the impact of the NVM programming model and persistent memory. Two movements are driving changes into the decades-old basic programming model. Block mode innovations include atomics, access hints, and NVM oriented operations. In addition, the emerging NVM technologies provide much higher…
August 13, 2013, Flash Memory Summit, Santa Clara, CA—Jason Taylor from Facebook described the structural and architectural implications of flash in the datacenter. Although bulk store is still in HDDs, newer use modes are making flash viable in longer term storage. Facebook has five main regional server centers and serves 84 percent of its members…
August 14, 2013, Flash Memory Summit, Santa Clara, CA—Swapna Yasarapu from STEC moderated a panel on SSD use cases and implementation. Panel members were George Crump from Storage Switzerland, Bruce Moxon from STEC, and Sean Stead from STEC. Stead provided an overview of flash in storage, including platforms and form factors, as well as the…
February 2013 – This years Solid State Circuit conference featured a processor session that was focusing on increasing cache size and more cores at low power. The rise in data size being handled by these units, has driven the systems to explore new architectures that are much more throughput oriented rather than MIPS/GFLOPs oriented. This…
January 29, 2013, SNIA Non-Volatile Memory Summit, Santa Clara, CA—Garret Swart from Oracle identified the potential benefits for applications with the new storage architectures. The different memory structures and performance levels calls for new programming styles. With the advent of DRAM-compatible NVM technologies, the choices for NVM, connectivity, and form factors allows for greater diversity…
August 28, 2012, Hot Chips Symposium, Cupertino, CA—This year’s Hot Chips key topic was power management. Intel, AMD, and MIPS all talked about re-architecting the cache controller to reduce misses and, as a result, greatly reduce power. Other major changes included new logic cells and significant architectural changes in other functional units. Power and performance…
August 2012 – At Siggraph, Fusion I/O was showing their new PCIe interface card that uses MLC Flash to create a cache for graphics operating software (called the IOFX card). Available now in a 420GB or 512GB configuration (with retail pricing starting at $2495USD) the board is targeted at accelerating large data tasks with a…
April 4,2011, Storage Network World, Santa Clara, Ca—Eason Ho from Calypso Systems described the emerging SNIA performance test specifications for solid state storage devices. The emerging market is over due for some standardization as there is no common methodology, terminology, nor test environment for SSDs. Because of the lack of standards, it is difficult to…