July 8, 2013, IMEC Technology Forum, San Francisco—Kurt Ronse from Imec talked about mastering patterning costs for future technology nodes. The biggest problems are that the technical requirements do not map well into any available technologies. Currently, 193 nm immersion lithography with multiple patterning is the workhorse technology. EUV is not ready for production, and…
December 1,2011, Printed Electronics USA 2011, Santa Clara, CA—Warren Jackson from HP talked about fabricating large area metal oxide thin film transistors (MOTFT) using roll-to-roll imprint lithography. These developments can be applied to many areas including displays, packaging, and civil and military functions. MOTFTs offer many advantages over amorphous silicon and poly-silicon. A-Si has low…
November 16, 2010, Santa Clara, CA—SFBA Nanotechnology Council held a symposium on “Nanoelectronics: Innovation and Implementation” at the National Semiconductor conference center. Chris Bencher, distinguished technical staff at Applied Materials talked about “Process and Integration-Based Scaling for 15 nm Nodes” in the opening session. First, he reviewed the progression of technologies for lithography. In the…