Mismatch in High-K Metal Gate Process Analog Design
December 16, 2014, IEDM, San Francisco—A. Woo from Broadcom presented their efforts in design techniques to compensate for mismatch in Hi-K metal gate processes. The optimization techniques include process, layout, and design for variability. Among the successful techniques that enhance traditional analog and RF functions in deep submicron technologies are: SoC re-architecting, digitally assisted ADC,…