Fast MRAM
February 24, 2015, ISSCC, San Francisco—Hiroki Noguchi from Toshiba highlighted their work on a 3.3 ns embedded STT-MRAM. The design uses a physically eliminated read-disturb scheme and a normally off architecture. Spin-torque transistor magnetic RAM development continues with efforts to overcome some key critical issues. The growth of last-level cache is helping to overcome the…