Common Platform – Arm
January 18, 2011, Common Platform Technology Forum, Santa Clara, CA– Mike Muller, CTO at ARM talked about scaling from dimensions of a cubic millimeter to a cubic kilometer. One of the problems with predicting technology changes is that most people get it wrong. An unusual example is someone who got it right.
In 1956, and AT&T person forecast everything about today’s smartphones. He suggested that people would have a number per person not per home, users would have customized ring tones, the network would be all electronic switching, and users would have what we now consider speed dial. Other aspects of the phone that we now consider normal include worldwide direct dialing, and video calling.
In other areas of computing, however, people to get things wrong. As computers evolved from mainframes, to mini-computers, to PCs, and to mobile platforms, people always thought the latest iteration was an end point. Now, we at least try to consider something will be the next Internet of things.
The drivers for all of these changes is always been increasing functionality and performance. In the PC era, cost also became a factor, the move to laptops added power consumption as a factor. Now mobile devices are given by function over energy and dollars. Optical scaling was responsible for many of these changes but stopped at 90 nm. Now scaling is becoming very uneven because shapes do not scale, and ultimately atoms do not scale at all. However, power per circuit used to scale as an inverse square of the area, but now only scales inversely to the area. Power density used to be a constant and now scales proportionally to area.
All of these changes and limits have forced manufacturers to innovate in materials, circuits, and processes. As the processes get more complex, more variables come into play. Now it’s necessary to the foundries to work with developers very early in the process development, so together they can create a PDK to compare against the silicon. Nevertheless, they still need silicon validation by creating a processor proof point. For the 20 nm process ARM developed an SOC with custom memory and oscillators from Cadence, standard cells characterized by Magma, and physical layout verified with Mentor tools.
Scaling doesn’t always mean much in their space. The ARM2 had 6000 gates in a 2 µ process. The cortex M0 consists of 8000 gates and an additional 20,000 gates for peripherals. Because the metrics are functionality divided by (available energy times cost), energy scavenging is a critical issue for pervasive devices. Industry needs breakthroughs in batteries and charging technologies to be able to meet user expectations.
In 2002, some of the applications or processors became part of a ubiquitous environment meeting to a need for 3-D stacks. One painting computer used solar cells as a processor on one level, sensors on another, and batteries on a third level. A similar three-level stack is used in measuring intra-ocular pressure, where a pressure sensor, solar cell, CPU, and battery are stacked in a 1 mm cube. Moving on, wireless sensors are now using different technologies and processes for each layer, so an sensor can be made in a 130 nm process, CPU in 65 nm, and memory in the smallest possible process available and connected in 3D.
PCs are also undergoing changes, to become portable. The computers are also moving into televisions because 3-D is not just pictures on a bigger screen. Everywhere embedded sensors are becoming part of the environment. These sensors facilitate and enable services. In the small form factors, computation and storage boost to the cloud. Services enable behavioral changes at the end of the value chain, when everything is connected inside of the smart home. The primary issues associated with these changes are privacy, care with data, and security.
At the other extreme is a nutrino detector in Antarctica. This is a 1 km³ active telescope. There are 70 boreholes that are 2 1/2 kilometers deep with 60 detectors in each hole starting at a depth of 1 1/2 km. This detector array is configured as one single parallel computer. Amdahl’s law states that the sequential paths are limiting factors in parallel computing. The hardware is the easy part, getting 4200 threads to synchronize across one computer is very hard.
The key to greater hardware and software efficiency is to reduce margins and architectural overhead. The software overhead can be minimized to be good enough to perform the function. The challenge of making higher efficiency devices is larger than any single company’s resources, so the ability to innovate quickly becomes a competitive advantage.
