IEDM 2012 – Ckt and Technology Interaction
December 2012 – San Francisco, CA – This year the International Electron Device Meeting kicked off with a short course on Circuit and Technology Interaction. Historically, this was held as several sessions in the conference focusing on the new devices for memories, logic and analog operation. With the overall shift to FDSOI and FinFET style devices as well as small geometry devices there are major changes to the chip architectures in addition to fine grained shifts in design. The paper sessions were handling the fine grained shifts in device stacking, biasing and applicability for the design blocks, and the architectural changes on the high level were addressed in the short course.
The course was broken down into several sections – High perfomrance microprocessors, Integrated systems for Mobile, Power and efficiency in nm CMOS, memory and DFM. The first portion set the theme for the session and identified that at nm level processes, the designs are Not digital, rather they are analog circuits all behaving in a non-ideal fashion. The designs methodologies have to not integrate new languages (such as Verilog-A) into the flow as awell as adding new validation steps to the process. These shifts to an analog methodology has the benefit of being able to directly model variability and impact of power turn-on and turn-off characteristics for power down, which is not possible in the pure digital domain. This also leads to the ability to analyze the leakage characteristic of the devices and minimize its impact on the overall circuit power. The short course dealt with a major issue at these nm processing and that is the scalability of the interconnect which is not longer following the Denard Device Scaling rules. The fallout was that the devices are essentially free, and as a result their use is not constrained not by the NFM and reliability of each device working, rather it is the probability and minimization of variation that generates statistics to the likelihood of correct performance.
IEDM 2012 – Taylor – Intel – Interconnect Scaling
Following the theme of power, the Mobile, Efficiency, and Memory sections dealt, for a majority of their slides on new needs for and techniques for on-chip temperature, power, and state measurement and monitoring. For the memories, it also discussed the struggles that arise from lowering power supplies, their impact on SNR and data recovery, and the reduced signal storage due to the small size of the devices. The IEDM conference has been detailing the plight of the Flash community, now down to a finite and countable number of electrons stored in a programed memory cell. This has lead to new circuits that include additional transistors and devices to insure that the information is stored and recovered properly from the cell. These memories include DRM, SRAM and Flash cells.
The mobile and power sections discussed not only device techniques but architectural and software level management of the power and the way that the blocks needed to incorporated into the SOC. The Design for manufacturing (DFM) section covered the variability and lithographic issues regarding the creation of pairs and groups for FinFETS and FDSOI devices. These are generally built not as single devices, but in blocks, and the variability is grouped.
