Multi-Media drives network and processor architecture
October 5, 2011 – San Jose, CA – The Linley Processor conference recently focused on new architectures and trends for network data processing. As video and multimedia have become more pervasive in all aspects of networking – wireless, content delivery, cloud storage & processing, and data center core applications. The larger data sized of this content, and the wide bandwidth that is required to provide the contents to multiple users at one time – without the benefit of multi-casting, has dramatically driven up the processing data rates required.
The shift from single core, single OS/process systems is on track to be surpassed by multi-core in early 2013. This delay in adoption, has to do mostly with replacement of existing systems as they follow their traditional lifecyle schedule. New systems that are being purchased now, are primarily multi-core with a minimum of dual-core configurations. Additionally, these processors when used at the front edges of the network, are running hypervisiors for virtualization, to give the concurrent users access to the network through a individualized core/memory/storage virtual machine. With this capability, there is a need for more data plane optimization and deep packet inspection in the networks with specialized hardware that is tuned to the task and more power efficient.
The conference was focused on platform products – the Cavium Basestation-on-a-Chip SOC the CNF71XX family processor, the Intel multi-core processor family, Netlogic’s XLP332 multi-core processor for 4G/LTE wireless, Freescale’s shift from a control/data plane architecture to a Linux kernel-based packet architecture and custom data plane accellerators from LSI, EZChip, Applied Micro, and Tilera. A big feature set of these cores, is the software control and configurablity. 6Wind, Intel and Freescale discussed SDKs for multi-core optimization and virtualization.
Intel – Data Plane Development offerings
On day 2, Orange discussed software defined networking for an agile processor architecture and MIPS, Applied Micro and AuthenTec discussed dedicated security hardware and virtualization. These security engines are typically blocks that are at the front end the data input to the multi-core processor. For cases like Netronome and Radisys which are involved with 100G data processing (flow processing and Deep Packet Inspection) the security engine is highly optimized for both power and performance to allow for the high speed data to be processed safely.
Xilinx Zynq EPP architecture
The software offerings for data plane optimization are avaialble from both Free and Commercial sources. Both solutions support migration over multi-core and over multiple processor families. The extension of the software based configuration is the Xilinx Zynq Extensible Processing Platform (EPP). The platform is not just an SOC or a standard product, but it instead has an ARM processing system, programmable logic, OS Kernel, libraries and APIs. applications, simulators, SW development tools SW & HW IP, and HW development tools. These software based platforms allow for the design implementation of complete low power solutions such as a single chip packet processor for Mobile Backhaul applications.
Mobile Backhaul built on Zynq EPP
The need to move multi-media has now irrevocably moved processing from single core to multi-core. This shift is now causing the software for both applications and the kernel level to be re-architected to work with the distributed processing cores and optimize memory use. This is leading to the multi-core designs supporting flexibility in final implementation that can be configured using the software. At this time the changes are one-time static, but dynamic & in-application reconfigurable designs are not to far off in the future.
